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5379c4a713
Haswell CPUs have special support for SHLD/SHRD with the same register for both sources. Such an instruction will go to the rotate/shift unit on port 0 or 6. This gives it 1 cycle latency and 0.5 cycle reciprocal throughput. When the register is not the same, it becomes a 3 cycle operation on port 1. Sandybridge and Ivybridge always have 1 cyc latency and 0.5 cycle reciprocal throughput for any SHLD. When FastSHLDRotate feature flag is set, we try to use SHLD for rotate by immediate unless BMI2 is enabled. But MachineCopyPropagation can look through a copy and change one of the sources to be different. This will break the hardware optimization. This patch adds psuedo instruction to hide the second source input until after register allocation and MachineCopyPropagation. I'm not sure if this is the best way to do this or if there's some other way we can make this work. Fixes PR41055 Differential Revision: https://reviews.llvm.org/D59391 llvm-svn: 357096
365 lines
8.4 KiB
LLVM
365 lines
8.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7 | FileCheck %s --check-prefix=ALL --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=corei7-avx | FileCheck %s --check-prefix=ALL --check-prefix=SHLD
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; RUN: llc < %s -mtriple=x86_64-- -mcpu=core-avx2 | FileCheck %s --check-prefix=ALL --check-prefix=BMI2
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define i64 @foo(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; ALL-LABEL: foo:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: movq %rdx, %rcx
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; ALL-NEXT: movq %rdi, %rax
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; ALL-NEXT: # kill: def $cl killed $cl killed $rcx
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; ALL-NEXT: rolq %cl, %rax
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; ALL-NEXT: retq
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entry:
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%0 = shl i64 %x, %z
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%1 = sub i64 64, %z
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%2 = lshr i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @bar(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; ALL-LABEL: bar:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: movq %rdx, %rcx
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; ALL-NEXT: movq %rsi, %rax
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; ALL-NEXT: # kill: def $cl killed $cl killed $rcx
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; ALL-NEXT: shldq %cl, %rdi, %rax
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; ALL-NEXT: retq
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entry:
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%0 = shl i64 %y, %z
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%1 = sub i64 64, %z
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%2 = lshr i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @un(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; ALL-LABEL: un:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: movq %rdx, %rcx
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; ALL-NEXT: movq %rdi, %rax
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; ALL-NEXT: # kill: def $cl killed $cl killed $rcx
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; ALL-NEXT: rorq %cl, %rax
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; ALL-NEXT: retq
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entry:
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%0 = lshr i64 %x, %z
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%1 = sub i64 64, %z
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%2 = shl i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @bu(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; ALL-LABEL: bu:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: movq %rdx, %rcx
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; ALL-NEXT: movq %rsi, %rax
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; ALL-NEXT: # kill: def $cl killed $cl killed $rcx
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; ALL-NEXT: shrdq %cl, %rdi, %rax
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; ALL-NEXT: retq
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entry:
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%0 = lshr i64 %y, %z
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%1 = sub i64 64, %z
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%2 = shl i64 %x, %1
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%3 = or i64 %2, %0
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ret i64 %3
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}
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define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; X64-LABEL: xfoo:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rolq $7, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: xfoo:
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; SHLD: # %bb.0: # %entry
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shldq $7, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: xfoo:
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; BMI2: # %bb.0: # %entry
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; BMI2-NEXT: rorxq $57, %rdi, %rax
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; BMI2-NEXT: retq
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entry:
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%0 = lshr i64 %x, 57
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%1 = shl i64 %x, 7
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @xfoop(i64* %p) nounwind readnone {
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; X64-LABEL: xfoop:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: rolq $7, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: xfoop:
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; SHLD: # %bb.0: # %entry
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; SHLD-NEXT: movq (%rdi), %rax
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; SHLD-NEXT: shldq $7, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: xfoop:
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; BMI2: # %bb.0: # %entry
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; BMI2-NEXT: rorxq $57, (%rdi), %rax
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; BMI2-NEXT: retq
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entry:
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%x = load i64, i64* %p
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%a = lshr i64 %x, 57
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%b = shl i64 %x, 7
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%c = or i64 %a, %b
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ret i64 %c
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}
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define i64 @xbar(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; ALL-LABEL: xbar:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: movq %rdi, %rax
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; ALL-NEXT: shrdq $57, %rsi, %rax
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; ALL-NEXT: retq
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entry:
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%0 = shl i64 %y, 7
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%1 = lshr i64 %x, 57
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; X64-LABEL: xun:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rolq $57, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: xun:
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; SHLD: # %bb.0: # %entry
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shldq $57, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: xun:
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; BMI2: # %bb.0: # %entry
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; BMI2-NEXT: rorxq $7, %rdi, %rax
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; BMI2-NEXT: retq
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entry:
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%0 = lshr i64 %x, 7
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%1 = shl i64 %x, 57
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @xunp(i64* %p) nounwind readnone {
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; X64-LABEL: xunp:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: rolq $57, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: xunp:
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; SHLD: # %bb.0: # %entry
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; SHLD-NEXT: movq (%rdi), %rax
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; SHLD-NEXT: shldq $57, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: xunp:
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; BMI2: # %bb.0: # %entry
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; BMI2-NEXT: rorxq $7, (%rdi), %rax
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; BMI2-NEXT: retq
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entry:
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%x = load i64, i64* %p
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%a = lshr i64 %x, 7
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%b = shl i64 %x, 57
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%c = or i64 %a, %b
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ret i64 %c
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}
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define i64 @xbu(i64 %x, i64 %y, i64 %z) nounwind readnone {
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; ALL-LABEL: xbu:
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; ALL: # %bb.0: # %entry
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; ALL-NEXT: movq %rdi, %rax
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; ALL-NEXT: shldq $57, %rsi, %rax
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; ALL-NEXT: retq
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entry:
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%0 = lshr i64 %y, 7
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%1 = shl i64 %x, 57
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%2 = or i64 %0, %1
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ret i64 %2
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}
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define i64 @fshl(i64 %x) nounwind {
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; X64-LABEL: fshl:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rolq $7, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshl:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shldq $7, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshl:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $57, %rdi, %rax
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; BMI2-NEXT: retq
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 7)
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ret i64 %f
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}
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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define i64 @fshl1(i64 %x) nounwind {
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; X64-LABEL: fshl1:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rolq %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshl1:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shldq $1, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshl1:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $63, %rdi, %rax
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; BMI2-NEXT: retq
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 1)
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ret i64 %f
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}
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define i64 @fshl63(i64 %x) nounwind {
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; X64-LABEL: fshl63:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rorq %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshl63:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shldq $63, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshl63:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $1, %rdi, %rax
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; BMI2-NEXT: retq
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 63)
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ret i64 %f
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}
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define i64 @fshl_load(i64* %p) nounwind {
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; X64-LABEL: fshl_load:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: rolq $7, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshl_load:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq (%rdi), %rax
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; SHLD-NEXT: shldq $7, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshl_load:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $57, (%rdi), %rax
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; BMI2-NEXT: retq
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%x = load i64, i64* %p
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%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 7)
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ret i64 %f
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}
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define i64 @fshr(i64 %x) nounwind {
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; X64-LABEL: fshr:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rorq $7, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshr:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shrdq $7, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshr:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $7, %rdi, %rax
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; BMI2-NEXT: retq
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 7)
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ret i64 %f
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}
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declare i64 @llvm.fshr.i64(i64, i64, i64)
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define i64 @fshr1(i64 %x) nounwind {
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; X64-LABEL: fshr1:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rorq %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshr1:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shrdq $1, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshr1:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $1, %rdi, %rax
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; BMI2-NEXT: retq
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 1)
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ret i64 %f
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}
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define i64 @fshr63(i64 %x) nounwind {
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; X64-LABEL: fshr63:
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; X64: # %bb.0:
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; X64-NEXT: movq %rdi, %rax
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; X64-NEXT: rolq %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshr63:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq %rdi, %rax
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; SHLD-NEXT: shrdq $63, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshr63:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $63, %rdi, %rax
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; BMI2-NEXT: retq
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 63)
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ret i64 %f
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}
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define i64 @fshr_load(i64* %p) nounwind {
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; X64-LABEL: fshr_load:
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; X64: # %bb.0:
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: rorq $7, %rax
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; X64-NEXT: retq
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;
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; SHLD-LABEL: fshr_load:
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; SHLD: # %bb.0:
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; SHLD-NEXT: movq (%rdi), %rax
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; SHLD-NEXT: shrdq $7, %rax, %rax
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; SHLD-NEXT: retq
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;
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; BMI2-LABEL: fshr_load:
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; BMI2: # %bb.0:
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; BMI2-NEXT: rorxq $7, (%rdi), %rax
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; BMI2-NEXT: retq
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%x = load i64, i64* %p
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%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 7)
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ret i64 %f
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}
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