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17f25ea47b
vextractf128 with 128-bit mem dest.
Combines
vextractf128 $0, %ymm0, %xmm0
vmovaps %xmm0, (%rdi)
to
vextractf128 $0, %ymm0, (%rdi)
rdar://11082570
llvm-svn: 153139
107 lines
3.6 KiB
LLVM
107 lines
3.6 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s
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; CHECK: @A
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; CHECK-NOT: vunpck
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; CHECK: vextractf128 $1
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define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 8, i32 8, i32 8>
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ret <8 x float> %shuffle
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}
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; CHECK: @B
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; CHECK-NOT: vunpck
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; CHECK: vextractf128 $1
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define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp {
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entry:
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%shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 4, i32 4>
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ret <4 x double> %shuffle
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}
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; CHECK: @t0
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vmovaps %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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define void @t0(float* nocapture %addr, <8 x float> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0)
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%1 = bitcast float* %addr to <4 x float>*
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store <4 x float> %0, <4 x float>* %1, align 16
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ret void
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}
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declare <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float>, i8) nounwind readnone
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; CHECK: @t1
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vmovups %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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define void @t1(float* %addr, <8 x float> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <4 x float> @llvm.x86.avx.vextractf128.ps.256(<8 x float> %a, i8 0)
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%1 = bitcast float* %addr to i8*
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tail call void @llvm.x86.sse.storeu.ps(i8* %1, <4 x float> %0)
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ret void
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}
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declare void @llvm.x86.sse.storeu.ps(i8*, <4 x float>) nounwind
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; CHECK: @t2
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vmovaps %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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define void @t2(double* nocapture %addr, <4 x double> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0)
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%1 = bitcast double* %addr to <2 x double>*
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store <2 x double> %0, <2 x double>* %1, align 16
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ret void
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}
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declare <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double>, i8) nounwind readnone
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; CHECK: @t3
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vmovups %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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define void @t3(double* %addr, <4 x double> %a) nounwind uwtable ssp {
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entry:
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%0 = tail call <2 x double> @llvm.x86.avx.vextractf128.pd.256(<4 x double> %a, i8 0)
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%1 = bitcast double* %addr to i8*
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tail call void @llvm.x86.sse2.storeu.pd(i8* %1, <2 x double> %0)
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ret void
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}
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declare void @llvm.x86.sse2.storeu.pd(i8*, <2 x double>) nounwind
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; CHECK: @t4
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vmovaps %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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define void @t4(<2 x i64>* nocapture %addr, <4 x i64> %a) nounwind uwtable ssp {
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
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%2 = bitcast <4 x i32> %1 to <2 x i64>
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store <2 x i64> %2, <2 x i64>* %addr, align 16
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ret void
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}
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declare <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32>, i8) nounwind readnone
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; CHECK: @t5
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; CHECK-NOT: vextractf128 $0, %ymm0, %xmm0
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; CHECK-NOT: vmovdqu %xmm0, (%rdi)
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; CHECK: vextractf128 $0, %ymm0, (%rdi)
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define void @t5(<2 x i64>* %addr, <4 x i64> %a) nounwind uwtable ssp {
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entry:
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%0 = bitcast <4 x i64> %a to <8 x i32>
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%1 = tail call <4 x i32> @llvm.x86.avx.vextractf128.si.256(<8 x i32> %0, i8 0)
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%2 = bitcast <2 x i64>* %addr to i8*
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%3 = bitcast <4 x i32> %1 to <16 x i8>
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tail call void @llvm.x86.sse2.storeu.dq(i8* %2, <16 x i8> %3)
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ret void
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}
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declare void @llvm.x86.sse2.storeu.dq(i8*, <16 x i8>) nounwind
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