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370 lines
17 KiB
TableGen
370 lines
17 KiB
TableGen
//===- HexagonIntrinsicsV4.td - V4 Instruction intrinsics --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This is populated based on the following specs:
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// Hexagon V4 Architecture Extensions
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// Application-Level Specification
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// 80-V9418-12 Rev. A
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// June 15, 2010
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//
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// ALU 32 types.
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//
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class si_ALU32_sisi_not<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class di_ALU32_s8si<string opc, Intrinsic IntID>
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: ALU32_rr<(outs DoubleRegs:$dst), (ins s8Imm:$src1, IntRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "(#$src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID imm:$src1, IntRegs:$src2))]>;
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class di_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs DoubleRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set DoubleRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class qi_neg_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_neg_ALU32_sis10<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, s10Imm:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class qi_neg_ALU32_siu9<string opc, Intrinsic IntID>
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: ALU32_rr<(outs PredRegs:$dst), (ins IntRegs:$src1, u9Imm:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class si_neg_ALU32_sisi<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class si_neg_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, #$src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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class si_ALU32_sis8<string opc, Intrinsic IntID>
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: ALU32_rr<(outs IntRegs:$dst), (ins IntRegs:$src1, s8Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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//
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// SInst Classes.
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//
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class qi_neg_SInst_qiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2),
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!strconcat("$dst = !", !strconcat(opc , "($src1, $src2)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2))]>;
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class qi_SInst_qi_andqiqi_neg<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, and($src2, !$src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class qi_SInst_qi_andqiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, and($src2, $src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class qi_SInst_qi_orqiqi_neg<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, or($src2, !$src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class qi_SInst_qi_orqiqi<string opc, Intrinsic IntID>
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: SInst<(outs PredRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, or($src2, $src3)")),
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[(set PredRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_si_addsis6<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s6Imm:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, add($src2, #$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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imm:$src3))]>;
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class si_SInst_si_subs6si<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s6Imm:$src2, IntRegs:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, sub(#$src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2,
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IntRegs:$src3))]>;
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class di_ALU64_didi_neg<string opc, Intrinsic IntID>
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: ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, DoubleRegs:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, ~$src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$src1, DoubleRegs:$src2))]>;
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class di_MInst_dididi_xacc<string opc, Intrinsic IntID>
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: MInst_acc<(outs DoubleRegs:$dst), (ins DoubleRegs:$dst2, DoubleRegs:$src1,
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DoubleRegs:$src2),
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!strconcat("$dst ^= ", !strconcat(opc , "($src1, $src2)")),
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[(set DoubleRegs:$dst, (IntID DoubleRegs:$dst2, DoubleRegs:$src1,
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DoubleRegs:$src2))],
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"$dst2 = $dst">;
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class si_MInst_sisisi_and<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst &= ", !strconcat(opc , "($src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_MInst_sisisi_andn<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst &= ", !strconcat(opc , "($src2, ~$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_sisis10_andi<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, IntRegs:$src2, s10Imm:$src3),
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!strconcat("$dst = ", !strconcat(opc ,
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"($src1, and($src2, #$src3))")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, IntRegs:$src2,
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imm:$src3))]>;
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class si_MInst_sisisi_xor<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst ^= ", !strconcat(opc , "($src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_MInst_sisisi_xorn<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst ^= ", !strconcat(opc , "($src2, ~$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_sisis10_or<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2, s10Imm:$src3),
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!strconcat("$dst |= ", !strconcat(opc , "($src2, #$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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imm:$src3))]>;
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class si_MInst_sisisi_or<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst |= ", !strconcat(opc , "($src2, $src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_MInst_sisisi_orn<string opc, Intrinsic IntID>
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: MInst<(outs IntRegs:$dst), (ins IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3),
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!strconcat("$dst |= ", !strconcat(opc , "($src2, ~$src3)")),
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[(set IntRegs:$dst, (IntID IntRegs:$dst1, IntRegs:$src2,
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IntRegs:$src3))]>;
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class si_SInst_siu5_sat<string opc, Intrinsic IntID>
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: SInst<(outs IntRegs:$dst), (ins IntRegs:$src1, u5Imm:$src2),
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!strconcat("$dst = ", !strconcat(opc , "($src1, #$src2):sat")),
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[(set IntRegs:$dst, (IntID IntRegs:$src1, imm:$src2))]>;
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/********************************************************************
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* ALU32/ALU *
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*********************************************************************/
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// ALU32 / ALU / Logical Operations.
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def Hexagon_A4_orn : si_ALU32_sisi_not <"or", int_hexagon_A4_orn>;
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def Hexagon_A4_andn : si_ALU32_sisi_not <"and", int_hexagon_A4_andn>;
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/********************************************************************
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* ALU32/PERM *
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*********************************************************************/
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// ALU32 / PERM / Combine Words Into Doublewords.
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def Hexagon_A4_combineir : di_ALU32_s8si <"combine", int_hexagon_A4_combineir>;
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def Hexagon_A4_combineri : di_ALU32_sis8 <"combine", int_hexagon_A4_combineri>;
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/********************************************************************
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* ALU32/PRED *
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*********************************************************************/
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// ALU32 / PRED / Conditional Shift Halfword.
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// ALU32 / PRED / Conditional Sign Extend.
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// ALU32 / PRED / Conditional Zero Extend.
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// ALU32 / PRED / Compare.
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def Hexagon_C4_cmpneq : qi_neg_ALU32_sisi <"cmp.eq", int_hexagon_C4_cmpneq>;
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def Hexagon_C4_cmpneqi : qi_neg_ALU32_sis10 <"cmp.eq", int_hexagon_C4_cmpneqi>;
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def Hexagon_C4_cmplte : qi_neg_ALU32_sisi <"cmp.gt", int_hexagon_C4_cmplte>;
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def Hexagon_C4_cmpltei : qi_neg_ALU32_sis10 <"cmp.gt", int_hexagon_C4_cmpltei>;
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def Hexagon_C4_cmplteu : qi_neg_ALU32_sisi <"cmp.gtu",int_hexagon_C4_cmplteu>;
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def Hexagon_C4_cmplteui: qi_neg_ALU32_siu9 <"cmp.gtu",int_hexagon_C4_cmplteui>;
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// ALU32 / PRED / cmpare To General Register.
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def Hexagon_A4_rcmpneq : si_neg_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpneq>;
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def Hexagon_A4_rcmpneqi: si_neg_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpneqi>;
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def Hexagon_A4_rcmpeq : si_ALU32_sisi <"cmp.eq", int_hexagon_A4_rcmpeq>;
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def Hexagon_A4_rcmpeqi : si_ALU32_sis8 <"cmp.eq", int_hexagon_A4_rcmpeqi>;
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/********************************************************************
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* CR *
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*********************************************************************/
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// CR / Corner Detection Acceleration.
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def Hexagon_C4_fastcorner9:
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qi_SInst_qiqi<"fastcorner9", int_hexagon_C4_fastcorner9>;
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def Hexagon_C4_fastcorner9_not:
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qi_neg_SInst_qiqi<"fastcorner9",int_hexagon_C4_fastcorner9_not>;
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// CR / Logical Operations On Predicates.
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def Hexagon_C4_and_andn:
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qi_SInst_qi_andqiqi_neg <"and", int_hexagon_C4_and_andn>;
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def Hexagon_C4_and_and:
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qi_SInst_qi_andqiqi <"and", int_hexagon_C4_and_and>;
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def Hexagon_C4_and_orn:
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qi_SInst_qi_orqiqi_neg <"and", int_hexagon_C4_and_orn>;
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def Hexagon_C4_and_or:
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qi_SInst_qi_orqiqi <"and", int_hexagon_C4_and_or>;
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def Hexagon_C4_or_andn:
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qi_SInst_qi_andqiqi_neg <"or", int_hexagon_C4_or_andn>;
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def Hexagon_C4_or_and:
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qi_SInst_qi_andqiqi <"or", int_hexagon_C4_or_and>;
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def Hexagon_C4_or_orn:
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qi_SInst_qi_orqiqi_neg <"or", int_hexagon_C4_or_orn>;
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def Hexagon_C4_or_or:
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qi_SInst_qi_orqiqi <"or", int_hexagon_C4_or_or>;
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/********************************************************************
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* XTYPE/ALU *
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*********************************************************************/
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// XTYPE / ALU / Add And Accumulate.
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def Hexagon_S4_addaddi:
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si_SInst_si_addsis6 <"add", int_hexagon_S4_addaddi>;
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def Hexagon_S4_subaddi:
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si_SInst_si_subs6si <"add", int_hexagon_S4_subaddi>;
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// XTYPE / ALU / Logical Doublewords.
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def Hexagon_S4_andnp:
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di_ALU64_didi_neg <"and", int_hexagon_A4_andnp>;
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def Hexagon_S4_ornp:
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di_ALU64_didi_neg <"or", int_hexagon_A4_ornp>;
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// XTYPE / ALU / Logical-logical Doublewords.
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def Hexagon_M4_xor_xacc:
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di_MInst_dididi_xacc <"xor", int_hexagon_M4_xor_xacc>;
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// XTYPE / ALU / Logical-logical Words.
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def HEXAGON_M4_and_and:
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si_MInst_sisisi_and <"and", int_hexagon_M4_and_and>;
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def HEXAGON_M4_and_or:
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si_MInst_sisisi_and <"or", int_hexagon_M4_and_or>;
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def HEXAGON_M4_and_xor:
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si_MInst_sisisi_and <"xor", int_hexagon_M4_and_xor>;
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def HEXAGON_M4_and_andn:
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si_MInst_sisisi_andn <"and", int_hexagon_M4_and_andn>;
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def HEXAGON_M4_xor_and:
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si_MInst_sisisi_xor <"and", int_hexagon_M4_xor_and>;
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def HEXAGON_M4_xor_or:
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si_MInst_sisisi_xor <"or", int_hexagon_M4_xor_or>;
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def HEXAGON_M4_xor_andn:
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si_MInst_sisisi_xorn <"and", int_hexagon_M4_xor_andn>;
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def HEXAGON_M4_or_and:
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si_MInst_sisisi_or <"and", int_hexagon_M4_or_and>;
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def HEXAGON_M4_or_or:
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si_MInst_sisisi_or <"or", int_hexagon_M4_or_or>;
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def HEXAGON_M4_or_xor:
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si_MInst_sisisi_or <"xor", int_hexagon_M4_or_xor>;
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def HEXAGON_M4_or_andn:
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si_MInst_sisisi_orn <"and", int_hexagon_M4_or_andn>;
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def HEXAGON_S4_or_andix:
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si_SInst_sisis10_andi <"or", int_hexagon_S4_or_andix>;
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def HEXAGON_S4_or_andi:
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si_SInst_sisis10_or <"and", int_hexagon_S4_or_andi>;
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def HEXAGON_S4_or_ori:
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si_SInst_sisis10_or <"or", int_hexagon_S4_or_ori>;
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// XTYPE / ALU / Modulo wrap.
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def HEXAGON_A4_modwrapu:
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si_ALU64_sisi <"modwrap", int_hexagon_A4_modwrapu>;
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// XTYPE / ALU / Round.
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def HEXAGON_A4_cround_ri:
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si_SInst_siu5 <"cround", int_hexagon_A4_cround_ri>;
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def HEXAGON_A4_cround_rr:
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si_SInst_sisi <"cround", int_hexagon_A4_cround_rr>;
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def HEXAGON_A4_round_ri:
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si_SInst_siu5 <"round", int_hexagon_A4_round_ri>;
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def HEXAGON_A4_round_rr:
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si_SInst_sisi <"round", int_hexagon_A4_round_rr>;
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def HEXAGON_A4_round_ri_sat:
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si_SInst_siu5_sat <"round", int_hexagon_A4_round_ri_sat>;
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def HEXAGON_A4_round_rr_sat:
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si_SInst_sisi_sat <"round", int_hexagon_A4_round_rr_sat>;
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// XTYPE / ALU / Vector reduce add unsigned halfwords.
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// XTYPE / ALU / Vector add bytes.
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// XTYPE / ALU / Vector conditional negate.
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// XTYPE / ALU / Vector maximum bytes.
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// XTYPE / ALU / Vector reduce maximum halfwords.
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// XTYPE / ALU / Vector reduce maximum words.
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// XTYPE / ALU / Vector minimum bytes.
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// XTYPE / ALU / Vector reduce minimum halfwords.
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// XTYPE / ALU / Vector reduce minimum words.
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// XTYPE / ALU / Vector subtract bytes.
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/********************************************************************
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* XTYPE/BIT *
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*********************************************************************/
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// XTYPE / BIT / Count leading.
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// XTYPE / BIT / Count trailing.
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// XTYPE / BIT / Extract bitfield.
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// XTYPE / BIT / Masked parity.
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// XTYPE / BIT / Bit reverse.
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// XTYPE / BIT / Split bitfield.
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/********************************************************************
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* XTYPE/COMPLEX *
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*********************************************************************/
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// XTYPE / COMPLEX / Complex add/sub halfwords.
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// XTYPE / COMPLEX / Complex add/sub words.
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// XTYPE / COMPLEX / Complex multiply 32x16.
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// XTYPE / COMPLEX / Vector reduce complex rotate.
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/********************************************************************
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* XTYPE/MPY *
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*********************************************************************/
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// XTYPE / COMPLEX / Complex add/sub halfwords.
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