mirror of
https://github.com/RPCS3/llvm-mirror.git
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b9c8074dcd
subtarget CPU descriptions and support new features of MachineScheduler. MachineModel has three categories of data: 1) Basic properties for coarse grained instruction cost model. 2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD). 3) Instruction itineraties for detailed per-cycle reservation tables. These will all live side-by-side. Any subtarget can use any combination of them. Instruction itineraries will not change in the near term. In the long run, I expect them to only be relevant for in-order VLIW machines that have complex contraints and require a precise scheduling/bundling model. Once itineraries are only actively used by VLIW-ish targets, they could be replaced by something more appropriate for those targets. This tablegen backend rewrite sets things up for introducing MachineModel type #2: per opcode/operand cost model. llvm-svn: 159891
482 lines
16 KiB
TableGen
482 lines
16 KiB
TableGen
//===-- X86Schedule.td - X86 Scheduling Definitions --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction Itinerary classes used for X86
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def IIC_DEFAULT : InstrItinClass;
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def IIC_ALU_MEM : InstrItinClass;
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def IIC_ALU_NONMEM : InstrItinClass;
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def IIC_LEA : InstrItinClass;
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def IIC_LEA_16 : InstrItinClass;
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def IIC_MUL8 : InstrItinClass;
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def IIC_MUL16_MEM : InstrItinClass;
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def IIC_MUL16_REG : InstrItinClass;
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def IIC_MUL32_MEM : InstrItinClass;
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def IIC_MUL32_REG : InstrItinClass;
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def IIC_MUL64 : InstrItinClass;
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// imul by al, ax, eax, tax
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def IIC_IMUL8 : InstrItinClass;
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def IIC_IMUL16_MEM : InstrItinClass;
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def IIC_IMUL16_REG : InstrItinClass;
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def IIC_IMUL32_MEM : InstrItinClass;
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def IIC_IMUL32_REG : InstrItinClass;
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def IIC_IMUL64 : InstrItinClass;
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// imul reg by reg|mem
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def IIC_IMUL16_RM : InstrItinClass;
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def IIC_IMUL16_RR : InstrItinClass;
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def IIC_IMUL32_RM : InstrItinClass;
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def IIC_IMUL32_RR : InstrItinClass;
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def IIC_IMUL64_RM : InstrItinClass;
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def IIC_IMUL64_RR : InstrItinClass;
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// imul reg = reg/mem * imm
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def IIC_IMUL16_RMI : InstrItinClass;
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def IIC_IMUL16_RRI : InstrItinClass;
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def IIC_IMUL32_RMI : InstrItinClass;
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def IIC_IMUL32_RRI : InstrItinClass;
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def IIC_IMUL64_RMI : InstrItinClass;
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def IIC_IMUL64_RRI : InstrItinClass;
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// div
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def IIC_DIV8_MEM : InstrItinClass;
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def IIC_DIV8_REG : InstrItinClass;
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def IIC_DIV16 : InstrItinClass;
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def IIC_DIV32 : InstrItinClass;
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def IIC_DIV64 : InstrItinClass;
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// idiv
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def IIC_IDIV8 : InstrItinClass;
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def IIC_IDIV16 : InstrItinClass;
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def IIC_IDIV32 : InstrItinClass;
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def IIC_IDIV64 : InstrItinClass;
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// neg/not/inc/dec
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def IIC_UNARY_REG : InstrItinClass;
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def IIC_UNARY_MEM : InstrItinClass;
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// add/sub/and/or/xor/adc/sbc/cmp/test
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def IIC_BIN_MEM : InstrItinClass;
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def IIC_BIN_NONMEM : InstrItinClass;
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// shift/rotate
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def IIC_SR : InstrItinClass;
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// shift double
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def IIC_SHD16_REG_IM : InstrItinClass;
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def IIC_SHD16_REG_CL : InstrItinClass;
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def IIC_SHD16_MEM_IM : InstrItinClass;
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def IIC_SHD16_MEM_CL : InstrItinClass;
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def IIC_SHD32_REG_IM : InstrItinClass;
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def IIC_SHD32_REG_CL : InstrItinClass;
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def IIC_SHD32_MEM_IM : InstrItinClass;
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def IIC_SHD32_MEM_CL : InstrItinClass;
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def IIC_SHD64_REG_IM : InstrItinClass;
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def IIC_SHD64_REG_CL : InstrItinClass;
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def IIC_SHD64_MEM_IM : InstrItinClass;
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def IIC_SHD64_MEM_CL : InstrItinClass;
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// cmov
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def IIC_CMOV16_RM : InstrItinClass;
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def IIC_CMOV16_RR : InstrItinClass;
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def IIC_CMOV32_RM : InstrItinClass;
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def IIC_CMOV32_RR : InstrItinClass;
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def IIC_CMOV64_RM : InstrItinClass;
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def IIC_CMOV64_RR : InstrItinClass;
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// set
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def IIC_SET_R : InstrItinClass;
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def IIC_SET_M : InstrItinClass;
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// jmp/jcc/jcxz
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def IIC_Jcc : InstrItinClass;
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def IIC_JCXZ : InstrItinClass;
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def IIC_JMP_REL : InstrItinClass;
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def IIC_JMP_REG : InstrItinClass;
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def IIC_JMP_MEM : InstrItinClass;
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def IIC_JMP_FAR_MEM : InstrItinClass;
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def IIC_JMP_FAR_PTR : InstrItinClass;
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// loop
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def IIC_LOOP : InstrItinClass;
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def IIC_LOOPE : InstrItinClass;
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def IIC_LOOPNE : InstrItinClass;
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// call
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def IIC_CALL_RI : InstrItinClass;
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def IIC_CALL_MEM : InstrItinClass;
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def IIC_CALL_FAR_MEM : InstrItinClass;
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def IIC_CALL_FAR_PTR : InstrItinClass;
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// ret
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def IIC_RET : InstrItinClass;
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def IIC_RET_IMM : InstrItinClass;
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//sign extension movs
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def IIC_MOVSX : InstrItinClass;
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def IIC_MOVSX_R16_R8 : InstrItinClass;
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def IIC_MOVSX_R16_M8 : InstrItinClass;
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def IIC_MOVSX_R16_R16 : InstrItinClass;
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def IIC_MOVSX_R32_R32 : InstrItinClass;
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//zero extension movs
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def IIC_MOVZX : InstrItinClass;
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def IIC_MOVZX_R16_R8 : InstrItinClass;
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def IIC_MOVZX_R16_M8 : InstrItinClass;
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def IIC_REP_MOVS : InstrItinClass;
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def IIC_REP_STOS : InstrItinClass;
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// SSE scalar/parallel binary operations
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def IIC_SSE_ALU_F32S_RR : InstrItinClass;
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def IIC_SSE_ALU_F32S_RM : InstrItinClass;
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def IIC_SSE_ALU_F64S_RR : InstrItinClass;
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def IIC_SSE_ALU_F64S_RM : InstrItinClass;
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def IIC_SSE_MUL_F32S_RR : InstrItinClass;
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def IIC_SSE_MUL_F32S_RM : InstrItinClass;
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def IIC_SSE_MUL_F64S_RR : InstrItinClass;
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def IIC_SSE_MUL_F64S_RM : InstrItinClass;
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def IIC_SSE_DIV_F32S_RR : InstrItinClass;
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def IIC_SSE_DIV_F32S_RM : InstrItinClass;
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def IIC_SSE_DIV_F64S_RR : InstrItinClass;
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def IIC_SSE_DIV_F64S_RM : InstrItinClass;
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def IIC_SSE_ALU_F32P_RR : InstrItinClass;
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def IIC_SSE_ALU_F32P_RM : InstrItinClass;
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def IIC_SSE_ALU_F64P_RR : InstrItinClass;
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def IIC_SSE_ALU_F64P_RM : InstrItinClass;
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def IIC_SSE_MUL_F32P_RR : InstrItinClass;
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def IIC_SSE_MUL_F32P_RM : InstrItinClass;
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def IIC_SSE_MUL_F64P_RR : InstrItinClass;
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def IIC_SSE_MUL_F64P_RM : InstrItinClass;
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def IIC_SSE_DIV_F32P_RR : InstrItinClass;
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def IIC_SSE_DIV_F32P_RM : InstrItinClass;
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def IIC_SSE_DIV_F64P_RR : InstrItinClass;
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def IIC_SSE_DIV_F64P_RM : InstrItinClass;
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def IIC_SSE_COMIS_RR : InstrItinClass;
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def IIC_SSE_COMIS_RM : InstrItinClass;
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def IIC_SSE_HADDSUB_RR : InstrItinClass;
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def IIC_SSE_HADDSUB_RM : InstrItinClass;
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def IIC_SSE_BIT_P_RR : InstrItinClass;
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def IIC_SSE_BIT_P_RM : InstrItinClass;
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def IIC_SSE_INTALU_P_RR : InstrItinClass;
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def IIC_SSE_INTALU_P_RM : InstrItinClass;
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def IIC_SSE_INTALUQ_P_RR : InstrItinClass;
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def IIC_SSE_INTALUQ_P_RM : InstrItinClass;
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def IIC_SSE_INTMUL_P_RR : InstrItinClass;
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def IIC_SSE_INTMUL_P_RM : InstrItinClass;
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def IIC_SSE_INTSH_P_RR : InstrItinClass;
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def IIC_SSE_INTSH_P_RM : InstrItinClass;
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def IIC_SSE_INTSH_P_RI : InstrItinClass;
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def IIC_SSE_CMPP_RR : InstrItinClass;
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def IIC_SSE_CMPP_RM : InstrItinClass;
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def IIC_SSE_SHUFP : InstrItinClass;
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def IIC_SSE_PSHUF : InstrItinClass;
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def IIC_SSE_UNPCK : InstrItinClass;
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def IIC_SSE_MOVMSK : InstrItinClass;
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def IIC_SSE_MASKMOV : InstrItinClass;
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def IIC_SSE_PEXTRW : InstrItinClass;
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def IIC_SSE_PINSRW : InstrItinClass;
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def IIC_SSE_PABS_RR : InstrItinClass;
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def IIC_SSE_PABS_RM : InstrItinClass;
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def IIC_SSE_SQRTP_RR : InstrItinClass;
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def IIC_SSE_SQRTP_RM : InstrItinClass;
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def IIC_SSE_SQRTS_RR : InstrItinClass;
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def IIC_SSE_SQRTS_RM : InstrItinClass;
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def IIC_SSE_RCPP_RR : InstrItinClass;
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def IIC_SSE_RCPP_RM : InstrItinClass;
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def IIC_SSE_RCPS_RR : InstrItinClass;
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def IIC_SSE_RCPS_RM : InstrItinClass;
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def IIC_SSE_MOV_S_RR : InstrItinClass;
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def IIC_SSE_MOV_S_RM : InstrItinClass;
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def IIC_SSE_MOV_S_MR : InstrItinClass;
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def IIC_SSE_MOVA_P_RR : InstrItinClass;
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def IIC_SSE_MOVA_P_RM : InstrItinClass;
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def IIC_SSE_MOVA_P_MR : InstrItinClass;
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def IIC_SSE_MOVU_P_RR : InstrItinClass;
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def IIC_SSE_MOVU_P_RM : InstrItinClass;
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def IIC_SSE_MOVU_P_MR : InstrItinClass;
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def IIC_SSE_MOVDQ : InstrItinClass;
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def IIC_SSE_MOVD_ToGP : InstrItinClass;
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def IIC_SSE_MOVQ_RR : InstrItinClass;
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def IIC_SSE_MOV_LH : InstrItinClass;
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def IIC_SSE_LDDQU : InstrItinClass;
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def IIC_SSE_MOVNT : InstrItinClass;
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def IIC_SSE_PHADDSUBD_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBD_RM : InstrItinClass;
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def IIC_SSE_PHADDSUBSW_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBSW_RM : InstrItinClass;
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def IIC_SSE_PHADDSUBW_RR : InstrItinClass;
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def IIC_SSE_PHADDSUBW_RM : InstrItinClass;
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def IIC_SSE_PSHUFB_RR : InstrItinClass;
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def IIC_SSE_PSHUFB_RM : InstrItinClass;
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def IIC_SSE_PSIGN_RR : InstrItinClass;
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def IIC_SSE_PSIGN_RM : InstrItinClass;
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def IIC_SSE_PMADD : InstrItinClass;
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def IIC_SSE_PMULHRSW : InstrItinClass;
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def IIC_SSE_PALIGNR : InstrItinClass;
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def IIC_SSE_MWAIT : InstrItinClass;
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def IIC_SSE_MONITOR : InstrItinClass;
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def IIC_SSE_PREFETCH : InstrItinClass;
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def IIC_SSE_PAUSE : InstrItinClass;
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def IIC_SSE_LFENCE : InstrItinClass;
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def IIC_SSE_MFENCE : InstrItinClass;
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def IIC_SSE_SFENCE : InstrItinClass;
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def IIC_SSE_LDMXCSR : InstrItinClass;
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def IIC_SSE_STMXCSR : InstrItinClass;
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def IIC_SSE_CVT_PD_RR : InstrItinClass;
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def IIC_SSE_CVT_PD_RM : InstrItinClass;
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def IIC_SSE_CVT_PS_RR : InstrItinClass;
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def IIC_SSE_CVT_PS_RM : InstrItinClass;
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def IIC_SSE_CVT_PI2PS_RR : InstrItinClass;
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def IIC_SSE_CVT_PI2PS_RM : InstrItinClass;
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def IIC_SSE_CVT_Scalar_RR : InstrItinClass;
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def IIC_SSE_CVT_Scalar_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI32_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI32_RR : InstrItinClass;
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def IIC_SSE_CVT_SS2SI64_RM : InstrItinClass;
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def IIC_SSE_CVT_SS2SI64_RR : InstrItinClass;
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def IIC_SSE_CVT_SD2SI_RM : InstrItinClass;
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def IIC_SSE_CVT_SD2SI_RR : InstrItinClass;
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// MMX
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def IIC_MMX_MOV_MM_RM : InstrItinClass;
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def IIC_MMX_MOV_REG_MM : InstrItinClass;
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def IIC_MMX_MOVQ_RM : InstrItinClass;
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def IIC_MMX_MOVQ_RR : InstrItinClass;
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def IIC_MMX_ALU_RM : InstrItinClass;
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def IIC_MMX_ALU_RR : InstrItinClass;
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def IIC_MMX_ALUQ_RM : InstrItinClass;
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def IIC_MMX_ALUQ_RR : InstrItinClass;
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def IIC_MMX_PHADDSUBW_RM : InstrItinClass;
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def IIC_MMX_PHADDSUBW_RR : InstrItinClass;
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def IIC_MMX_PHADDSUBD_RM : InstrItinClass;
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def IIC_MMX_PHADDSUBD_RR : InstrItinClass;
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def IIC_MMX_PMUL : InstrItinClass;
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def IIC_MMX_MISC_FUNC_MEM : InstrItinClass;
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def IIC_MMX_MISC_FUNC_REG : InstrItinClass;
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def IIC_MMX_PSADBW : InstrItinClass;
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def IIC_MMX_SHIFT_RI : InstrItinClass;
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def IIC_MMX_SHIFT_RM : InstrItinClass;
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def IIC_MMX_SHIFT_RR : InstrItinClass;
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def IIC_MMX_UNPCK_H_RM : InstrItinClass;
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def IIC_MMX_UNPCK_H_RR : InstrItinClass;
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def IIC_MMX_UNPCK_L : InstrItinClass;
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def IIC_MMX_PCK_RM : InstrItinClass;
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def IIC_MMX_PCK_RR : InstrItinClass;
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def IIC_MMX_PSHUF : InstrItinClass;
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def IIC_MMX_PEXTR : InstrItinClass;
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def IIC_MMX_PINSRW : InstrItinClass;
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def IIC_MMX_MASKMOV : InstrItinClass;
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def IIC_MMX_CVT_PD_RR : InstrItinClass;
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def IIC_MMX_CVT_PD_RM : InstrItinClass;
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def IIC_MMX_CVT_PS_RR : InstrItinClass;
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def IIC_MMX_CVT_PS_RM : InstrItinClass;
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def IIC_CMPX_LOCK : InstrItinClass;
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def IIC_CMPX_LOCK_8 : InstrItinClass;
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def IIC_CMPX_LOCK_8B : InstrItinClass;
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def IIC_CMPX_LOCK_16B : InstrItinClass;
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def IIC_XADD_LOCK_MEM : InstrItinClass;
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def IIC_XADD_LOCK_MEM8 : InstrItinClass;
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def IIC_FILD : InstrItinClass;
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def IIC_FLD : InstrItinClass;
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def IIC_FLD80 : InstrItinClass;
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def IIC_FST : InstrItinClass;
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def IIC_FST80 : InstrItinClass;
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def IIC_FIST : InstrItinClass;
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def IIC_FLDZ : InstrItinClass;
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def IIC_FUCOM : InstrItinClass;
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def IIC_FUCOMI : InstrItinClass;
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def IIC_FCOMI : InstrItinClass;
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def IIC_FNSTSW : InstrItinClass;
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def IIC_FNSTCW : InstrItinClass;
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def IIC_FLDCW : InstrItinClass;
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def IIC_FNINIT : InstrItinClass;
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def IIC_FFREE : InstrItinClass;
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def IIC_FNCLEX : InstrItinClass;
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def IIC_WAIT : InstrItinClass;
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def IIC_FXAM : InstrItinClass;
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def IIC_FNOP : InstrItinClass;
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def IIC_FLDL : InstrItinClass;
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def IIC_F2XM1 : InstrItinClass;
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def IIC_FYL2X : InstrItinClass;
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def IIC_FPTAN : InstrItinClass;
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def IIC_FPATAN : InstrItinClass;
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def IIC_FXTRACT : InstrItinClass;
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def IIC_FPREM1 : InstrItinClass;
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def IIC_FPSTP : InstrItinClass;
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def IIC_FPREM : InstrItinClass;
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def IIC_FYL2XP1 : InstrItinClass;
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def IIC_FSINCOS : InstrItinClass;
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def IIC_FRNDINT : InstrItinClass;
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def IIC_FSCALE : InstrItinClass;
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def IIC_FCOMPP : InstrItinClass;
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def IIC_FXSAVE : InstrItinClass;
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def IIC_FXRSTOR : InstrItinClass;
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def IIC_FXCH : InstrItinClass;
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// System instructions
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def IIC_CPUID : InstrItinClass;
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def IIC_INT : InstrItinClass;
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def IIC_INT3 : InstrItinClass;
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def IIC_INVD : InstrItinClass;
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def IIC_INVLPG : InstrItinClass;
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def IIC_IRET : InstrItinClass;
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def IIC_HLT : InstrItinClass;
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def IIC_LXS : InstrItinClass;
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def IIC_LTR : InstrItinClass;
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def IIC_RDTSC : InstrItinClass;
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def IIC_RSM : InstrItinClass;
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def IIC_SIDT : InstrItinClass;
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def IIC_SGDT : InstrItinClass;
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def IIC_SLDT : InstrItinClass;
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def IIC_STR : InstrItinClass;
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def IIC_SWAPGS : InstrItinClass;
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def IIC_SYSCALL : InstrItinClass;
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def IIC_SYS_ENTER_EXIT : InstrItinClass;
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def IIC_IN_RR : InstrItinClass;
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def IIC_IN_RI : InstrItinClass;
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def IIC_OUT_RR : InstrItinClass;
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def IIC_OUT_IR : InstrItinClass;
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def IIC_INS : InstrItinClass;
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def IIC_MOV_REG_DR : InstrItinClass;
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def IIC_MOV_DR_REG : InstrItinClass;
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def IIC_MOV_REG_CR : InstrItinClass;
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def IIC_MOV_CR_REG : InstrItinClass;
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def IIC_MOV_REG_SR : InstrItinClass;
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def IIC_MOV_MEM_SR : InstrItinClass;
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def IIC_MOV_SR_REG : InstrItinClass;
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def IIC_MOV_SR_MEM : InstrItinClass;
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def IIC_LAR_RM : InstrItinClass;
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def IIC_LAR_RR : InstrItinClass;
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def IIC_LSL_RM : InstrItinClass;
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def IIC_LSL_RR : InstrItinClass;
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def IIC_LGDT : InstrItinClass;
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def IIC_LIDT : InstrItinClass;
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def IIC_LLDT_REG : InstrItinClass;
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def IIC_LLDT_MEM : InstrItinClass;
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def IIC_PUSH_CS : InstrItinClass;
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def IIC_PUSH_SR : InstrItinClass;
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def IIC_POP_SR : InstrItinClass;
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def IIC_POP_SR_SS : InstrItinClass;
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def IIC_VERR : InstrItinClass;
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def IIC_VERW_REG : InstrItinClass;
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def IIC_VERW_MEM : InstrItinClass;
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def IIC_WRMSR : InstrItinClass;
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def IIC_RDMSR : InstrItinClass;
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def IIC_RDPMC : InstrItinClass;
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def IIC_SMSW : InstrItinClass;
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def IIC_LMSW_REG : InstrItinClass;
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def IIC_LMSW_MEM : InstrItinClass;
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def IIC_ENTER : InstrItinClass;
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def IIC_LEAVE : InstrItinClass;
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def IIC_POP_MEM : InstrItinClass;
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def IIC_POP_REG16 : InstrItinClass;
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def IIC_POP_REG : InstrItinClass;
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def IIC_POP_F : InstrItinClass;
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def IIC_POP_FD : InstrItinClass;
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def IIC_POP_A : InstrItinClass;
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def IIC_PUSH_IMM : InstrItinClass;
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def IIC_PUSH_MEM : InstrItinClass;
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def IIC_PUSH_REG : InstrItinClass;
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def IIC_PUSH_F : InstrItinClass;
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def IIC_PUSH_A : InstrItinClass;
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def IIC_BSWAP : InstrItinClass;
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|
def IIC_BSF : InstrItinClass;
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def IIC_BSR : InstrItinClass;
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def IIC_MOVS : InstrItinClass;
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def IIC_STOS : InstrItinClass;
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|
def IIC_SCAS : InstrItinClass;
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|
def IIC_CMPS : InstrItinClass;
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|
def IIC_MOV : InstrItinClass;
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|
def IIC_MOV_MEM : InstrItinClass;
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|
def IIC_AHF : InstrItinClass;
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|
def IIC_BT_MI : InstrItinClass;
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|
def IIC_BT_MR : InstrItinClass;
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|
def IIC_BT_RI : InstrItinClass;
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|
def IIC_BT_RR : InstrItinClass;
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|
def IIC_BTX_MI : InstrItinClass;
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|
def IIC_BTX_MR : InstrItinClass;
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|
def IIC_BTX_RI : InstrItinClass;
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|
def IIC_BTX_RR : InstrItinClass;
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|
def IIC_XCHG_REG : InstrItinClass;
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|
def IIC_XCHG_MEM : InstrItinClass;
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|
def IIC_XADD_REG : InstrItinClass;
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|
def IIC_XADD_MEM : InstrItinClass;
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|
def IIC_CMPXCHG_MEM : InstrItinClass;
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|
def IIC_CMPXCHG_REG : InstrItinClass;
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|
def IIC_CMPXCHG_MEM8 : InstrItinClass;
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|
def IIC_CMPXCHG_REG8 : InstrItinClass;
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|
def IIC_CMPXCHG_8B : InstrItinClass;
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|
def IIC_CMPXCHG_16B : InstrItinClass;
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|
def IIC_LODS : InstrItinClass;
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|
def IIC_OUTS : InstrItinClass;
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|
def IIC_CLC : InstrItinClass;
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|
def IIC_CLD : InstrItinClass;
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|
def IIC_CLI : InstrItinClass;
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|
def IIC_CMC : InstrItinClass;
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|
def IIC_CLTS : InstrItinClass;
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|
def IIC_STC : InstrItinClass;
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|
def IIC_STI : InstrItinClass;
|
|
def IIC_STD : InstrItinClass;
|
|
def IIC_XLAT : InstrItinClass;
|
|
def IIC_AAA : InstrItinClass;
|
|
def IIC_AAD : InstrItinClass;
|
|
def IIC_AAM : InstrItinClass;
|
|
def IIC_AAS : InstrItinClass;
|
|
def IIC_DAA : InstrItinClass;
|
|
def IIC_DAS : InstrItinClass;
|
|
def IIC_BOUND : InstrItinClass;
|
|
def IIC_ARPL_REG : InstrItinClass;
|
|
def IIC_ARPL_MEM : InstrItinClass;
|
|
def IIC_MOVBE : InstrItinClass;
|
|
|
|
def IIC_NOP : InstrItinClass;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Processor instruction itineraries.
|
|
|
|
// IssueWidth is analagous to the number of decode units. Core and its
|
|
// descendents, including Nehalem and SandyBridge have 4 decoders.
|
|
// Resources beyond the decoder operate on micro-ops and are bufferred
|
|
// so adjacent micro-ops don't directly compete.
|
|
//
|
|
// MinLatency=0 indicates that RAW dependencies can be decoded in the
|
|
// same cycle.
|
|
//
|
|
// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
|
|
// indicates high latency opcodes. Alternatively, InstrItinData
|
|
// entries may be included here to define specific operand
|
|
// latencies. Since these latencies are not used for pipeline hazards,
|
|
// they do not need to be exact.
|
|
//
|
|
// The GenericModel contains no instruciton itineraries.
|
|
def GenericModel : SchedMachineModel {
|
|
let IssueWidth = 4;
|
|
let MinLatency = 0;
|
|
let LoadLatency = 4;
|
|
let HighLatency = 10;
|
|
}
|
|
|
|
include "X86ScheduleAtom.td"
|