Reid Kleckner 74bbf4a42b [IR] Split out target specific intrinsic enums into separate headers ... This has two main effects: - Optimizes debug info size by saving 221.86 MB of obj file size in a Windows optimized+debug build of 'all'. This is 3.03% of 7,332.7MB of object file size. - Incremental step towards decoupling target intrinsics. The enums are still compact, so adding and removing a single target-specific intrinsic will trigger a rebuild of all of LLVM. Assigning distinct target id spaces is potential future work. Part of PR34259 Reviewers: efriedma, echristo, MaskRay Reviewed By: echristo, MaskRay Differential Revision: https://reviews.llvm.org/D71320		2019-12-11 18:02:14 -08:00
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AsmParser	[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"	2019-11-21 10:48:08 -08:00
Disassembler	[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"	2019-11-21 10:48:08 -08:00
MCTargetDesc	[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"	2019-11-21 10:48:08 -08:00
TargetInfo	[cmake] Explicitly mark libraries defined in lib/ as "Component Libraries"	2019-11-21 10:48:08 -08:00
BitTracker.cpp	Use MCRegister in MCRegisterInfo's interfaces	2019-08-02 20:23:00 +00:00
BitTracker.h
CMakeLists.txt
Hexagon.h
Hexagon.td
HexagonAsmPrinter.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonAsmPrinter.h
HexagonBitSimplify.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonBitTracker.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonBitTracker.h
HexagonBlockRanges.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
HexagonBlockRanges.h
HexagonBranchRelaxation.cpp	[Alignment][NFC] Remove unneeded llvm:: scoping on Align types	2019-09-27 12:54:21 +00:00
HexagonCallingConv.td
HexagonCFGOptimizer.cpp
HexagonCommonGEP.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonConstExtenders.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonConstPropagation.cpp	Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'	2019-11-23 23:09:39 +01:00
HexagonCopyToCombine.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonDepArch.h
HexagonDepArch.td
HexagonDepDecoders.inc
HexagonDepIICHVX.td
HexagonDepIICScalar.td
HexagonDepInstrFormats.td
HexagonDepInstrInfo.td
HexagonDepITypes.h
HexagonDepITypes.td
HexagonDepMapAsm2Intrin.td	Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"	2019-09-19 16:26:14 +00:00
HexagonDepMappings.td
HexagonDepOperands.td	Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"	2019-09-19 16:26:14 +00:00
HexagonDepTimingClasses.h
HexagonEarlyIfConv.cpp	Hexagon - fix uninitialized variable warnings. NFCI.	2019-11-14 14:21:16 +00:00
HexagonExpandCondsets.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonFixupHwLoops.cpp	[Alignment][NFC] Remove unneeded llvm:: scoping on Align types	2019-09-27 12:54:21 +00:00
HexagonFrameLowering.cpp	[Hexagon] Fix vector spill expansion to use proper alignment	2019-11-12 09:43:21 -06:00
HexagonFrameLowering.h	Use Align for TFL::TransientStackAlignment	2019-10-21 08:31:25 +00:00
HexagonGenExtract.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonGenInsert.cpp	Reland 'Fixed -Wdeprecated-copy warnings. NFCI.'	2019-11-23 23:09:39 +01:00
HexagonGenMux.cpp	[Hexagon] Validate the iterators before converting them to mux.	2019-11-14 13:01:16 -06:00
HexagonGenPredicate.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonHardwareLoops.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonHazardRecognizer.cpp
HexagonHazardRecognizer.h
HexagonIICHVX.td
HexagonIICScalar.td
HexagonInstrFormats.td
HexagonInstrFormatsV5.td
HexagonInstrFormatsV60.td
HexagonInstrFormatsV65.td
HexagonInstrInfo.cpp	[Hexagon] Fix vector spill expansion to use proper alignment	2019-11-12 09:43:21 -06:00
HexagonInstrInfo.h	Use MCRegister in copyPhysReg	2019-11-11 14:42:33 +05:30
HexagonIntrinsics.td	[Hexagon] Remove incorrect intrinsic definition and invalid testcase	2019-11-21 09:18:15 -06:00
HexagonIntrinsicsV5.td
HexagonIntrinsicsV60.td
HexagonISelDAGToDAG.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonISelDAGToDAG.h	[Hexagon] Update PS_aligna with max stack alignment once isel completes	2019-11-12 11:47:29 -06:00
HexagonISelDAGToDAGHVX.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonISelLowering.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonISelLowering.h	DAG: Add function context to isFMAFasterThanFMulAndFAdd	2019-11-19 19:25:26 +05:30
HexagonISelLoweringHVX.cpp	[Hexagon] Generate vector min/max for HVX	2019-08-15 16:13:17 +00:00
HexagonLoopIdiomRecognition.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonMachineFunctionInfo.cpp
HexagonMachineFunctionInfo.h
HexagonMachineScheduler.cpp
HexagonMachineScheduler.h
HexagonMapAsm2IntrinV62.gen.td
HexagonMapAsm2IntrinV65.gen.td
HexagonMCInstLower.cpp
HexagonNewValueJump.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonOperands.td
HexagonOptAddrMode.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonOptimizeSZextends.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonPatterns.td	Fix pattern error for S2_tstbit_i instruction	2019-10-30 11:21:48 -05:00
HexagonPatternsHVX.td	[Hexagon] Bitcast v4i16 to v8i8, unify no-op casts between scalar and HVX	2019-09-23 14:33:27 +00:00
HexagonPatternsV65.td
HexagonPeephole.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonPseudo.td	[Hexagon] Fix vector spill expansion to use proper alignment	2019-11-12 09:43:21 -06:00
HexagonRDFOpt.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonRegisterInfo.cpp	[Hexagon] Fix vector spill expansion to use proper alignment	2019-11-12 09:43:21 -06:00
HexagonRegisterInfo.h
HexagonRegisterInfo.td
HexagonSchedule.td
HexagonScheduleV5.td
HexagonScheduleV55.td
HexagonScheduleV60.td
HexagonScheduleV62.td
HexagonScheduleV65.td
HexagonScheduleV66.td
HexagonSelectionDAGInfo.cpp
HexagonSelectionDAGInfo.h
HexagonSplitConst32AndConst64.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonSplitDouble.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
HexagonStoreWidening.cpp	Sink all InitializePasses.h includes	2019-11-13 16:34:37 -08:00
HexagonSubtarget.cpp	Use a bit of relaxed constexpr to make FeatureBitset costant intializable	2019-08-24 15:02:44 +00:00
HexagonSubtarget.h	[SVE][MVT] Fixed-length vector MVT ranges	2019-09-17 10:19:23 +00:00
HexagonTargetMachine.cpp	[llvm] Migrate llvm::make_unique to std::make_unique	2019-08-15 15:54:37 +00:00
HexagonTargetMachine.h
HexagonTargetObjectFile.cpp	OpaquePtr: switch to GlobalValue::getValueType in a few places. NFC.	2019-07-11 13:13:02 +00:00
HexagonTargetObjectFile.h
HexagonTargetStreamer.h
HexagonTargetTransformInfo.cpp	[ARM] Teach the Arm cost model that a Shift can be folded into other instructions	2019-12-09 10:24:33 +00:00
HexagonTargetTransformInfo.h	[ARM] Teach the Arm cost model that a Shift can be folded into other instructions	2019-12-09 10:24:33 +00:00
HexagonVectorLoopCarriedReuse.cpp	[IR] Split out target specific intrinsic enums into separate headers	2019-12-11 18:02:14 -08:00
HexagonVectorPrint.cpp
HexagonVExtract.cpp	[Hexagon] Handle stack realignment in hexagon-vextract	2019-11-12 09:43:21 -06:00
HexagonVLIWPacketizer.cpp	Hexagon - fix uninitialized variable warnings. NFCI.	2019-11-14 14:21:16 +00:00
HexagonVLIWPacketizer.h	Prune two MachineInstr.h includes, fix up deps	2019-10-19 00:22:07 +00:00
LLVMBuild.txt
RDFCopy.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
RDFCopy.h
RDFDeadCode.cpp	Prune two MachineInstr.h includes, fix up deps	2019-10-19 00:22:07 +00:00
RDFDeadCode.h
RDFGraph.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
RDFGraph.h
RDFLiveness.cpp	Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVM	2019-08-15 19:22:08 +00:00
RDFLiveness.h
RDFRegisters.cpp	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00
RDFRegisters.h	Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC	2019-08-01 23:27:28 +00:00