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https://github.com/RPCS3/llvm-mirror.git
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df2896d609
llvm-svn: 81290
49 lines
1.1 KiB
LLVM
49 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=x86-64 | grep {movzbl %\[abcd\]h,} | count 4
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; RUN: llc < %s -march=x86 > %t
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; RUN: grep {incb %ah} %t | count 3
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; RUN: grep {movzbl %ah,} %t | count 3
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; Use h registers. On x86-64, codegen doesn't support general allocation
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; of h registers yet, due to x86 encoding complications.
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define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
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%t0 = lshr i64 %x, 8
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%t1 = trunc i64 %t0 to i8
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%t2 = add i8 %t1, 1
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store i8 %t2, i8* %p
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ret void
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}
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define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
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%t0 = lshr i32 %x, 8
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%t1 = trunc i32 %t0 to i8
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%t2 = add i8 %t1, 1
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store i8 %t2, i8* %p
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ret void
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}
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define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
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%t0 = lshr i16 %x, 8
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%t1 = trunc i16 %t0 to i8
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%t2 = add i8 %t1, 1
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store i8 %t2, i8* %p
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ret void
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}
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define i64 @qux64(i64 inreg %x) nounwind {
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%t0 = lshr i64 %x, 8
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%t1 = and i64 %t0, 255
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ret i64 %t1
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}
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define i32 @qux32(i32 inreg %x) nounwind {
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%t0 = lshr i32 %x, 8
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%t1 = and i32 %t0, 255
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ret i32 %t1
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}
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define i16 @qux16(i16 inreg %x) nounwind {
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%t0 = lshr i16 %x, 8
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ret i16 %t0
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}
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