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c14a1eda84
The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
94 lines
2.8 KiB
LLVM
94 lines
2.8 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx,+sse2 | FileCheck %s
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; There are no MMX operations here, so we use XMM or i64.
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define void @ti8(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to <8 x i8>
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%tmp2 = bitcast double %b to <8 x i8>
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%tmp3 = add <8 x i8> %tmp1, %tmp2
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; CHECK: paddb %xmm1, %xmm0
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store <8 x i8> %tmp3, <8 x i8>* null
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ret void
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}
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define void @ti16(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to <4 x i16>
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%tmp2 = bitcast double %b to <4 x i16>
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%tmp3 = add <4 x i16> %tmp1, %tmp2
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; CHECK: paddw %xmm1, %xmm0
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store <4 x i16> %tmp3, <4 x i16>* null
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ret void
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}
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define void @ti32(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to <2 x i32>
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%tmp2 = bitcast double %b to <2 x i32>
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%tmp3 = add <2 x i32> %tmp1, %tmp2
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; CHECK: paddd %xmm1, %xmm0
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store <2 x i32> %tmp3, <2 x i32>* null
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ret void
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}
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define void @ti64(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to <1 x i64>
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%tmp2 = bitcast double %b to <1 x i64>
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%tmp3 = add <1 x i64> %tmp1, %tmp2
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; CHECK: addq %rax, %rcx
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store <1 x i64> %tmp3, <1 x i64>* null
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ret void
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}
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; MMX intrinsics calls get us MMX instructions.
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define void @ti8a(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to x86_mmx
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; CHECK: movdq2q
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%tmp2 = bitcast double %b to x86_mmx
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; CHECK: movdq2q
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%tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.b(x86_mmx %tmp1, x86_mmx %tmp2)
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store x86_mmx %tmp3, x86_mmx* null
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ret void
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}
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define void @ti16a(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to x86_mmx
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; CHECK: movdq2q
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%tmp2 = bitcast double %b to x86_mmx
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; CHECK: movdq2q
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%tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.w(x86_mmx %tmp1, x86_mmx %tmp2)
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store x86_mmx %tmp3, x86_mmx* null
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ret void
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}
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define void @ti32a(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to x86_mmx
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; CHECK: movdq2q
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%tmp2 = bitcast double %b to x86_mmx
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; CHECK: movdq2q
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%tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.d(x86_mmx %tmp1, x86_mmx %tmp2)
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store x86_mmx %tmp3, x86_mmx* null
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ret void
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}
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define void @ti64a(double %a, double %b) nounwind {
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entry:
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%tmp1 = bitcast double %a to x86_mmx
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; CHECK: movdq2q
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%tmp2 = bitcast double %b to x86_mmx
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; CHECK: movdq2q
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%tmp3 = tail call x86_mmx @llvm.x86.mmx.padd.q(x86_mmx %tmp1, x86_mmx %tmp2)
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store x86_mmx %tmp3, x86_mmx* null
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ret void
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}
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declare x86_mmx @llvm.x86.mmx.padd.b(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.w(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.d(x86_mmx, x86_mmx)
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declare x86_mmx @llvm.x86.mmx.padd.q(x86_mmx, x86_mmx)
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