mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 12:12:47 +01:00
97a8fdc19c
(sbbl x, x) sets the registers to 0 or ~0. Combined with two's complement arithmetic, we can fold the intermediate AND and the ADD into a single SUB. This fixes <rdar://problem/8449754>. llvm-svn: 114460
15 lines
344 B
LLVM
15 lines
344 B
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s
|
|
; <rdar://problem/8449754>
|
|
|
|
define i32 @add32carry(i32 %sum, i32 %x) nounwind readnone ssp {
|
|
entry:
|
|
; CHECK: sbbl %ecx, %ecx
|
|
; CHECK-NOT: addl
|
|
; CHECK: subl %ecx, %eax
|
|
%add4 = add i32 %x, %sum
|
|
%cmp = icmp ult i32 %add4, %x
|
|
%inc = zext i1 %cmp to i32
|
|
%z.0 = add i32 %add4, %inc
|
|
ret i32 %z.0
|
|
}
|