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c14a1eda84
The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
33 lines
1.2 KiB
LLVM
33 lines
1.2 KiB
LLVM
; RUN: llc < %s -march=x86 -mattr=+mmx | grep psllq | grep 32
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; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psllq | grep 32
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; RUN: llc < %s -march=x86 -mattr=+mmx | grep psrad
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; RUN: llc < %s -march=x86-64 -mattr=+mmx | grep psrlw
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define i64 @t1(<1 x i64> %mm1) nounwind {
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entry:
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%tmp = bitcast <1 x i64> %mm1 to x86_mmx
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%tmp6 = tail call x86_mmx @llvm.x86.mmx.pslli.q( x86_mmx %tmp, i32 32 ) ; <x86_mmx> [#uses=1]
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%retval1112 = bitcast x86_mmx %tmp6 to i64
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ret i64 %retval1112
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}
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declare x86_mmx @llvm.x86.mmx.pslli.q(x86_mmx, i32) nounwind readnone
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define i64 @t2(x86_mmx %mm1, x86_mmx %mm2) nounwind {
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entry:
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%tmp7 = tail call x86_mmx @llvm.x86.mmx.psra.d( x86_mmx %mm1, x86_mmx %mm2 ) nounwind readnone ; <x86_mmx> [#uses=1]
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%retval1112 = bitcast x86_mmx %tmp7 to i64
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ret i64 %retval1112
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}
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declare x86_mmx @llvm.x86.mmx.psra.d(x86_mmx, x86_mmx) nounwind readnone
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define i64 @t3(x86_mmx %mm1, i32 %bits) nounwind {
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entry:
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%tmp8 = tail call x86_mmx @llvm.x86.mmx.psrli.w( x86_mmx %mm1, i32 %bits ) nounwind readnone ; <x86_mmx> [#uses=1]
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%retval1314 = bitcast x86_mmx %tmp8 to i64
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ret i64 %retval1314
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}
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declare x86_mmx @llvm.x86.mmx.psrli.w(x86_mmx, i32) nounwind readnone
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