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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
108 lines
3.5 KiB
C++
108 lines
3.5 KiB
C++
//===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower RISCV MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
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const AsmPrinter &AP) {
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MCContext &Ctx = AP.OutContext;
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RISCVMCExpr::VariantKind Kind;
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switch (MO.getTargetFlags()) {
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default:
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llvm_unreachable("Unknown target flag on GV operand");
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case RISCVII::MO_None:
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Kind = RISCVMCExpr::VK_RISCV_None;
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break;
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case RISCVII::MO_LO:
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Kind = RISCVMCExpr::VK_RISCV_LO;
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break;
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case RISCVII::MO_HI:
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Kind = RISCVMCExpr::VK_RISCV_HI;
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break;
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}
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const MCExpr *ME =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
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if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
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ME = MCBinaryExpr::createAdd(
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ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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if (Kind != RISCVMCExpr::VK_RISCV_None)
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ME = RISCVMCExpr::create(ME, Kind, Ctx);
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return MCOperand::createExpr(ME);
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}
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bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp,
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const AsmPrinter &AP) {
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switch (MO.getType()) {
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default:
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report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::createReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, AP.getSymbol(MO.getGlobal()), AP);
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = lowerSymbolOperand(
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MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(
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MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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break;
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}
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return true;
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}
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void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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const AsmPrinter &AP) {
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OutMI.setOpcode(MI->getOpcode());
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for (const MachineOperand &MO : MI->operands()) {
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MCOperand MCOp;
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if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
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OutMI.addOperand(MCOp);
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}
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}
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