mirror of
https://github.com/RPCS3/llvm-mirror.git
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757d898c4f
Summary: The updated tests were previously infallible because the SIMD bitwise operations do not contain vector types in their names. Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D51369 llvm-svn: 340858
441 lines
14 KiB
LLVM
441 lines
14 KiB
LLVM
; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -wasm-enable-unimplemented-simd -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,SIMD128-VM
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; RUN: llc < %s -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=-simd128 -fast-isel --show-mc-encoding | FileCheck %s --check-prefixes CHECK,NO-SIMD128
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; Test that basic SIMD128 arithmetic operations assemble as expected.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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; ==============================================================================
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; 16 x i8
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; ==============================================================================
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; CHECK-LABEL: add_v16i8
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.add $push0=, $0, $1 # encoding: [0xfd,0x18]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @add_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = add <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: sub_v16i8
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.sub $push0=, $0, $1 # encoding: [0xfd,0x1c]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @sub_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = sub <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: mul_v16i8
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; NO-SIMD128-NOT: i8x16
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i8x16.mul $push0=, $0, $1 # encoding: [0xfd,0x20]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @mul_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = mul <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: and_v16i8
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.and $push0=, $0, $1 # encoding: [0xfd,0x3b]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @and_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = and <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: or_v16i8
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.or $push0=, $0, $1 # encoding: [0xfd,0x3c]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @or_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = or <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: xor_v16i8
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @xor_v16i8(<16 x i8> %x, <16 x i8> %y) {
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%a = xor <16 x i8> %x, %y
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ret <16 x i8> %a
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}
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; CHECK-LABEL: not_v16i8
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
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; SIMD128: return $pop0 #
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define <16 x i8> @not_v16i8(<16 x i8> %x) {
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%a = xor <16 x i8> %x, <i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1,
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i8 -1, i8 -1, i8 -1, i8 -1>
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ret <16 x i8> %a
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}
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; ==============================================================================
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; 8 x i16
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; ==============================================================================
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; CHECK-LABEL: add_v8i16
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.add $push0=, $0, $1 # encoding: [0xfd,0x19]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @add_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = add <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: sub_v8i16
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.sub $push0=, $0, $1 # encoding: [0xfd,0x1d]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @sub_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = sub <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: mul_v8i16
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; NO-SIMD128-NOT: i16x8
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i16x8.mul $push0=, $0, $1 # encoding: [0xfd,0x21]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @mul_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = mul <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: and_v8i16
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.and $push0=, $0, $1 # encoding: [0xfd,0x3b]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @and_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = and <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: or_v8i16
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.or $push0=, $0, $1 # encoding: [0xfd,0x3c]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @or_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = or <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: xor_v8i16
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @xor_v8i16(<8 x i16> %x, <8 x i16> %y) {
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%a = xor <8 x i16> %x, %y
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ret <8 x i16> %a
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}
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; CHECK-LABEL: not_v8i16
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
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; SIMD128: return $pop0 #
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define <8 x i16> @not_v8i16(<8 x i16> %x) {
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%a = xor <8 x i16> %x, <i16 -1, i16 -1, i16 -1, i16 -1,
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i16 -1, i16 -1, i16 -1, i16 -1>
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ret <8 x i16> %a
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}
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; ==============================================================================
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; 4 x i32
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; ==============================================================================
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; CHECK-LABEL: add_v4i32
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.add $push0=, $0, $1 # encoding: [0xfd,0x1a]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @add_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = add <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: sub_v4i32
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x1e]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @sub_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = sub <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: mul_v4i32
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; NO-SIMD128-NOT: i32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x22]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @mul_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = mul <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: and_v4i32
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.and $push0=, $0, $1 # encoding: [0xfd,0x3b]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @and_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = and <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: or_v4i32
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.or $push0=, $0, $1 # encoding: [0xfd,0x3c]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @or_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = or <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: xor_v4i32
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @xor_v4i32(<4 x i32> %x, <4 x i32> %y) {
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%a = xor <4 x i32> %x, %y
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ret <4 x i32> %a
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}
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; CHECK-LABEL: not_v4i32
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; NO-SIMD128-NOT: v128
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; SIMD128: .param v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
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; SIMD128: return $pop0 #
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define <4 x i32> @not_v4i32(<4 x i32> %x) {
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%a = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>
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ret <4 x i32> %a
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}
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; ==============================================================================
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; 2 x i64
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; ==============================================================================
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; CHECK-LABEL: add_v2i64
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.add $push0=, $0, $1 # encoding: [0xfd,0x1b]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @add_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = add <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: sub_v2i64
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: i64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x1f]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @sub_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = sub <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; v2i64.mul is not in spec
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; CHECK-LABEL: mul_v2i64
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; NO-SIMD128-NOT: i64x2
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; SIMD128-VM-NOT: i64x2
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; SIMD128-NOT: i64x2.mul
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; SIMD128: i64x2.extract_lane
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; SIMD128: i64.mul
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define <2 x i64> @mul_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = mul <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: and_v2i64
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; NO-SIMD128-NOT: v128
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; SIMD128-VM-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.and $push0=, $0, $1 # encoding: [0xfd,0x3b]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @and_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = and <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: or_v2i64
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; NO-SIMD128-NOT: v128
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; SIMD128-VM-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.or $push0=, $0, $1 # encoding: [0xfd,0x3c]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @or_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = or <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: xor_v2i64
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; NO-SIMD128-NOT: v128
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; SIMD128-VM-NOT: v128
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.xor $push0=, $0, $1 # encoding: [0xfd,0x3d]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @xor_v2i64(<2 x i64> %x, <2 x i64> %y) {
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%a = xor <2 x i64> %x, %y
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ret <2 x i64> %a
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}
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; CHECK-LABEL: not_v2i64
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; NO-SIMD128-NOT: v128
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; SIMD128-VM-NOT: v128
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; SIMD128: .param v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: v128.not $push0=, $0 # encoding: [0xfd,0x3e]{{$}}
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; SIMD128: return $pop0 #
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define <2 x i64> @not_v2i64(<2 x i64> %x) {
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%a = xor <2 x i64> %x, <i64 -1, i64 -1>
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ret <2 x i64> %a
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}
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; ==============================================================================
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; 4 x float
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; ==============================================================================
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; CHECK-LABEL: add_v4f32
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.add $push0=, $0, $1 # encoding: [0xfd,0x7a]{{$}}
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; SIMD128: return $pop0 #
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define <4 x float> @add_v4f32(<4 x float> %x, <4 x float> %y) {
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%a = fadd <4 x float> %x, %y
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ret <4 x float> %a
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}
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; CHECK-LABEL: sub_v4f32
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; NO-SIMD128-NOT: f32x4
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; SIMD128: .param v128, v128{{$}}
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; SIMD128: .result v128{{$}}
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; SIMD128: f32x4.sub $push0=, $0, $1 # encoding: [0xfd,0x7c]{{$}}
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; SIMD128: return $pop0 #
|
|
define <4 x float> @sub_v4f32(<4 x float> %x, <4 x float> %y) {
|
|
%a = fsub <4 x float> %x, %y
|
|
ret <4 x float> %a
|
|
}
|
|
|
|
; CHECK-LABEL: div_v4f32
|
|
; NO-SIMD128-NOT: f32x4
|
|
; SIMD128: .param v128, v128{{$}}
|
|
; SIMD128: .result v128{{$}}
|
|
; SIMD128: f32x4.div $push0=, $0, $1 # encoding: [0xfd,0x7e]{{$}}
|
|
; SIMD128: return $pop0 #
|
|
define <4 x float> @div_v4f32(<4 x float> %x, <4 x float> %y) {
|
|
%a = fdiv <4 x float> %x, %y
|
|
ret <4 x float> %a
|
|
}
|
|
|
|
; CHECK-LABEL: mul_v4f32
|
|
; NO-SIMD128-NOT: f32x4
|
|
; SIMD128: .param v128, v128{{$}}
|
|
; SIMD128: .result v128{{$}}
|
|
; SIMD128: f32x4.mul $push0=, $0, $1 # encoding: [0xfd,0x80]{{$}}
|
|
; SIMD128: return $pop0 #
|
|
define <4 x float> @mul_v4f32(<4 x float> %x, <4 x float> %y) {
|
|
%a = fmul <4 x float> %x, %y
|
|
ret <4 x float> %a
|
|
}
|
|
|
|
; ==============================================================================
|
|
; 2 x double
|
|
; ==============================================================================
|
|
; CHECK-LABEL: add_v2f64
|
|
; NO-SIMD128-NOT: f64x2
|
|
; SIMD129-VM-NOT: f62x2
|
|
; SIMD128: .param v128, v128{{$}}
|
|
; SIMD128: .result v128{{$}}
|
|
; SIMD128: f64x2.add $push0=, $0, $1 # encoding: [0xfd,0x7b]{{$}}
|
|
; SIMD128: return $pop0 #
|
|
define <2 x double> @add_v2f64(<2 x double> %x, <2 x double> %y) {
|
|
%a = fadd <2 x double> %x, %y
|
|
ret <2 x double> %a
|
|
}
|
|
|
|
; CHECK-LABEL: sub_v2f64
|
|
; NO-SIMD128-NOT: f64x2
|
|
; SIMD129-VM-NOT: f62x2
|
|
; SIMD128: .param v128, v128{{$}}
|
|
; SIMD128: .result v128{{$}}
|
|
; SIMD128: f64x2.sub $push0=, $0, $1 # encoding: [0xfd,0x7d]{{$}}
|
|
; SIMD128: return $pop0 #
|
|
define <2 x double> @sub_v2f64(<2 x double> %x, <2 x double> %y) {
|
|
%a = fsub <2 x double> %x, %y
|
|
ret <2 x double> %a
|
|
}
|
|
|
|
; CHECK-LABEL: div_v2f64
|
|
; NO-SIMD128-NOT: f64x2
|
|
; SIMD129-VM-NOT: f62x2
|
|
; SIMD128: .param v128, v128{{$}}
|
|
; SIMD128: .result v128{{$}}
|
|
; SIMD128: f64x2.div $push0=, $0, $1 # encoding: [0xfd,0x7f]{{$}}
|
|
; SIMD128: return $pop0 #
|
|
define <2 x double> @div_v2f64(<2 x double> %x, <2 x double> %y) {
|
|
%a = fdiv <2 x double> %x, %y
|
|
ret <2 x double> %a
|
|
}
|
|
|
|
; CHECK-LABEL: mul_v2f64
|
|
; NO-SIMD128-NOT: f64x2
|
|
; SIMD129-VM-NOT: f62x2
|
|
; SIMD128: .param v128, v128{{$}}
|
|
; SIMD128: .result v128{{$}}
|
|
; SIMD128: f64x2.mul $push0=, $0, $1 # encoding: [0xfd,0x81]{{$}}
|
|
; SIMD128: return $pop0 #
|
|
define <2 x double> @mul_v2f64(<2 x double> %x, <2 x double> %y) {
|
|
%a = fmul <2 x double> %x, %y
|
|
ret <2 x double> %a
|
|
}
|