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https://github.com/RPCS3/llvm-mirror.git
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6d5f31ab18
Summary: Nodes that have no uses are eventually pruned when they are selected from the worklist. Record nodes newly added to the worklist or DAG and perform pruning after every combine attempt. Reviewers: efriedma, RKSimon, craig.topper, spatel, jyknight Reviewed By: jyknight Subscribers: jdoerfert, jyknight, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D58070 llvm-svn: 357283
576 lines
20 KiB
LLVM
576 lines
20 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
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declare i32 @llvm.r600.read.tidig.x() #0
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; FUNC-LABEL: {{^}}test2:
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; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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define amdgpu_kernel void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <2 x i32>, <2 x i32> addrspace(1)* %in, i32 1
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%a = load <2 x i32>, <2 x i32> addrspace(1) * %in
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%b = load <2 x i32>, <2 x i32> addrspace(1) * %b_ptr
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%result = and <2 x i32> %a, %b
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store <2 x i32> %result, <2 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}test4:
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; EG: AND_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
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; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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; SI: s_and_b32 s{{[0-9]+, s[0-9]+, s[0-9]+}}
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define amdgpu_kernel void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
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%b_ptr = getelementptr <4 x i32>, <4 x i32> addrspace(1)* %in, i32 1
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%a = load <4 x i32>, <4 x i32> addrspace(1) * %in
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%b = load <4 x i32>, <4 x i32> addrspace(1) * %b_ptr
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%result = and <4 x i32> %a, %b
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store <4 x i32> %result, <4 x i32> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i32:
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; SI: s_and_b32
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define amdgpu_kernel void @s_and_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i32:
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687
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define amdgpu_kernel void @s_and_constant_i32(i32 addrspace(1)* %out, i32 %a) {
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%and = and i32 %a, 1234567
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FIXME: We should really duplicate the constant so that the SALU use
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; can fold into the s_and_b32 and the VALU one is materialized
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; directly without copying from the SGPR.
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; Second use is a VGPR use of the constant.
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; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_0:
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; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687
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; SI-DAG: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
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; SI-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], [[K]]
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; SI: buffer_store_dword [[VK]]
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define amdgpu_kernel void @s_and_multi_use_constant_i32_0(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%and = and i32 %a, 1234567
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; Just to stop future replacement of copy to vgpr + store with VALU op.
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%foo = add i32 %and, %b
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store volatile i32 %foo, i32 addrspace(1)* %out
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store volatile i32 1234567, i32 addrspace(1)* %out
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ret void
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}
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; Second use is another SGPR use of the constant.
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; FUNC-LABEL: {{^}}s_and_multi_use_constant_i32_1:
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; SI: s_mov_b32 [[K:s[0-9]+]], 0x12d687
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; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, [[K]]
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; SI: s_add_i32
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; SI: s_add_i32 [[ADD:s[0-9]+]], s{{[0-9]+}}, [[K]]
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; SI: v_mov_b32_e32 [[VADD:v[0-9]+]], [[ADD]]
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; SI: buffer_store_dword [[VADD]]
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define amdgpu_kernel void @s_and_multi_use_constant_i32_1(i32 addrspace(1)* %out, i32 %a, i32 %b) {
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%and = and i32 %a, 1234567
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%foo = add i32 %and, 1234567
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%bar = add i32 %foo, %b
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store volatile i32 %bar, i32 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i32_vgpr_vgpr:
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; SI: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define amdgpu_kernel void @v_and_i32_vgpr_vgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
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%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep.a
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%b = load i32, i32 addrspace(1)* %gep.b
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i32_sgpr_vgpr:
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; SI-DAG: s_load_dword [[SA:s[0-9]+]]
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; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]]
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; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
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define amdgpu_kernel void @v_and_i32_sgpr_vgpr(i32 addrspace(1)* %out, i32 %a, i32 addrspace(1)* %bptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep.b = getelementptr i32, i32 addrspace(1)* %bptr, i32 %tid
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%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%b = load i32, i32 addrspace(1)* %gep.b
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i32_vgpr_sgpr:
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; SI-DAG: s_load_dword [[SA:s[0-9]+]]
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; SI-DAG: {{buffer|flat}}_load_dword [[VB:v[0-9]+]]
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; SI: v_and_b32_e32 v{{[0-9]+}}, [[SA]], [[VB]]
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define amdgpu_kernel void @v_and_i32_vgpr_sgpr(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 %b) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep.a = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%gep.out = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep.a
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%and = and i32 %a, %b
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store i32 %and, i32 addrspace(1)* %gep.out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_constant_i32
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; SI: v_and_b32_e32 v{{[0-9]+}}, 0x12d687, v{{[0-9]+}}
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define amdgpu_kernel void @v_and_constant_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep, align 4
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%and = and i32 %a, 1234567
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_inline_imm_64_i32
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; SI: v_and_b32_e32 v{{[0-9]+}}, 64, v{{[0-9]+}}
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define amdgpu_kernel void @v_and_inline_imm_64_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep, align 4
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%and = and i32 %a, 64
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_inline_imm_neg_16_i32
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; SI: v_and_b32_e32 v{{[0-9]+}}, -16, v{{[0-9]+}}
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define amdgpu_kernel void @v_and_inline_imm_neg_16_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep = getelementptr i32, i32 addrspace(1)* %aptr, i32 %tid
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%a = load i32, i32 addrspace(1)* %gep, align 4
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%and = and i32 %a, -16
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store i32 %and, i32 addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i64
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; SI: s_and_b64
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define amdgpu_kernel void @s_and_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%and = and i64 %a, %b
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_i1:
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; SI: s_load_dword [[LOAD:s[0-9]+]]
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; SI: s_lshr_b32 [[B_SHIFT:s[0-9]+]], [[LOAD]], 8
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; SI: s_and_b32 [[AND:s[0-9]+]], [[LOAD]], [[B_SHIFT]]
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; SI: s_and_b32 [[AND_TRUNC:s[0-9]+]], [[AND]], 1{{$}}
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; SI: v_mov_b32_e32 [[V_AND_TRUNC:v[0-9]+]], [[AND_TRUNC]]
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; SI: buffer_store_byte [[V_AND_TRUNC]]
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define amdgpu_kernel void @s_and_i1(i1 addrspace(1)* %out, i1 %a, i1 %b) {
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%and = and i1 %a, %b
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store i1 %and, i1 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_constant_i64:
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; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000{{$}}
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; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80{{$}}
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; SI: buffer_store_dwordx2
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define amdgpu_kernel void @s_and_constant_i64(i64 addrspace(1)* %out, i64 %a) {
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%and = and i64 %a, 549756338176
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_multi_use_constant_i64:
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; XSI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x80000{{$}}
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; XSI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0x80{{$}}
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; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[KLO]]:[[KHI]]{{\]}}
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define amdgpu_kernel void @s_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 %a, i64 %b) {
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%and0 = and i64 %a, 549756338176
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%and1 = and i64 %b, 549756338176
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store volatile i64 %and0, i64 addrspace(1)* %out
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store volatile i64 %and1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_32_bit_constant_i64:
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x12d687{{$}}
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define amdgpu_kernel void @s_and_32_bit_constant_i64(i64 addrspace(1)* %out, i32, i64 %a) {
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%and = and i64 %a, 1234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}s_and_multi_use_inline_imm_i64:
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; SI: s_load_dwordx2
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; SI: s_load_dword [[A:s[0-9]+]]
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; SI: s_load_dword [[B:s[0-9]+]]
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; SI: s_load_dwordx2
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; SI-NOT: and
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; SI: s_lshl_b32 [[A]], [[A]], 1
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; SI: s_lshl_b32 [[B]], [[B]], 1
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; SI: s_and_b32 s{{[0-9]+}}, [[A]], 62
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; SI: s_and_b32 s{{[0-9]+}}, [[B]], 62
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; SI-NOT: and
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; SI: buffer_store_dwordx2
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define amdgpu_kernel void @s_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i32, i64 %a, i32, i64 %b, i32, i64 %c) {
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%shl.a = shl i64 %a, 1
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%shl.b = shl i64 %b, 1
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%and0 = and i64 %shl.a, 62
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%and1 = and i64 %shl.b, 62
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%add0 = add i64 %and0, %c
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%add1 = add i64 %and1, %c
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store volatile i64 %add0, i64 addrspace(1)* %out
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store volatile i64 %add1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_i64:
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; SI: v_and_b32
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; SI: v_and_b32
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define amdgpu_kernel void @v_and_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 addrspace(1)* %bptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
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%a = load i64, i64 addrspace(1)* %gep.a, align 8
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%gep.b = getelementptr i64, i64 addrspace(1)* %bptr, i32 %tid
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%b = load i64, i64 addrspace(1)* %gep.b, align 8
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%and = and i64 %a, %b
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_constant_i64:
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0xab19b207, {{v[0-9]+}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, 0x11e, {{v[0-9]+}}
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; SI: buffer_store_dwordx2
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define amdgpu_kernel void @v_and_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%tid = call i32 @llvm.r600.read.tidig.x() #0
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%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
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%a = load i64, i64 addrspace(1)* %gep.a, align 8
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%and = and i64 %a, 1231231234567
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store i64 %and, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_multi_use_constant_i64:
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; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}}
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; SI-DAG: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}}
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; SI-DAG: s_movk_i32 [[KHI:s[0-9]+]], 0x11e{{$}}
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; SI-DAG: s_mov_b32 [[KLO:s[0-9]+]], 0xab19b207{{$}}
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO0]]
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI0]]
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KLO]], v[[LO1]]
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; SI-DAG: v_and_b32_e32 {{v[0-9]+}}, [[KHI]], v[[HI1]]
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; SI: buffer_store_dwordx2
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; SI: buffer_store_dwordx2
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define amdgpu_kernel void @v_and_multi_use_constant_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
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%a = load volatile i64, i64 addrspace(1)* %aptr
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%b = load volatile i64, i64 addrspace(1)* %aptr
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%and0 = and i64 %a, 1231231234567
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%and1 = and i64 %b, 1231231234567
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store volatile i64 %and0, i64 addrspace(1)* %out
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store volatile i64 %and1, i64 addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_and_multi_use_inline_imm_i64:
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; SI: buffer_load_dwordx2 v{{\[}}[[LO0:[0-9]+]]:[[HI0:[0-9]+]]{{\]}}
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; SI-NOT: and
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; SI: buffer_load_dwordx2 v{{\[}}[[LO1:[0-9]+]]:[[HI1:[0-9]+]]{{\]}}
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; SI-NOT: and
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; SI: v_and_b32_e32 v[[RESLO0:[0-9]+]], 63, v[[LO0]]
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; SI: v_and_b32_e32 v[[RESLO1:[0-9]+]], 63, v[[LO1]]
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; SI-NOT: and
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO0]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO1]]
|
|
define amdgpu_kernel void @v_and_multi_use_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
|
%a = load volatile i64, i64 addrspace(1)* %aptr
|
|
%b = load volatile i64, i64 addrspace(1)* %aptr
|
|
%and0 = and i64 %a, 63
|
|
%and1 = and i64 %b, 63
|
|
store volatile i64 %and0, i64 addrspace(1)* %out
|
|
store volatile i64 %and1, i64 addrspace(1)* %out
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}v_and_i64_32_bit_constant:
|
|
; SI: {{buffer|flat}}_load_dword [[VAL:v[0-9]+]]
|
|
; SI-NOT: and
|
|
; SI: v_and_b32_e32 {{v[0-9]+}}, 0x12d687, [[VAL]]
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @v_and_i64_32_bit_constant(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
|
%and = and i64 %a, 1234567
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}v_and_inline_imm_i64:
|
|
; SI: {{buffer|flat}}_load_dword v{{[0-9]+}}
|
|
; SI-NOT: and
|
|
; SI: v_and_b32_e32 {{v[0-9]+}}, 64, {{v[0-9]+}}
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @v_and_inline_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
|
%and = and i64 %a, 64
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Should be able to reduce load width
|
|
; FUNC-LABEL: {{^}}v_and_inline_neg_imm_i64:
|
|
; SI: {{buffer|flat}}_load_dwordx2 v{{\[}}[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]{{\]}}
|
|
; SI-NOT: and
|
|
; SI: v_and_b32_e32 v[[VAL_LO]], -8, v[[VAL_LO]]
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2 v{{\[}}[[VAL_LO]]:[[VAL_HI]]{{\]}}
|
|
define amdgpu_kernel void @v_and_inline_neg_imm_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr) {
|
|
%tid = call i32 @llvm.r600.read.tidig.x() #0
|
|
%gep.a = getelementptr i64, i64 addrspace(1)* %aptr, i32 %tid
|
|
%a = load i64, i64 addrspace(1)* %gep.a, align 8
|
|
%and = and i64 %a, -8
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 64
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dword
|
|
define amdgpu_kernel void @s_and_inline_imm_64_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 64
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_64_i64_noshrink:
|
|
; SI: s_load_dword [[A:s[0-9]+]]
|
|
; SI: s_lshl_b32 [[A]], [[A]], 1{{$}}
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s{{[0-9]+}}, [[A]], 64
|
|
; SI-NOT: and
|
|
; SI: s_add_u32
|
|
; SI-NEXT: s_addc_u32
|
|
define amdgpu_kernel void @s_and_inline_imm_64_i64_noshrink(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a, i32, i64 %b) {
|
|
%shl = shl i64 %a, 1
|
|
%and = and i64 %shl, 64
|
|
%add = add i64 %and, %b
|
|
store i64 %add, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_1_i64
|
|
; SI: s_load_dwordx2
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_1_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 1
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_1.0_i64
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 1.0
|
|
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3ff00000
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 4607182418800017408
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_1.0_i64
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -1.0
|
|
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbff00000
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_1.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 13830554455654793216
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_0.5_i64
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0.5
|
|
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x3fe00000
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 4602678819172646912
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_0.5_i64:
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -0.5
|
|
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xbfe00000
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_0.5_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 13826050856027422720
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_2.0_i64:
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 2.0
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 4611686018427387904
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_2.0_i64:
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, -2.0
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_2.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 13835058055282163712
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_4.0_i64:
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 4.0
|
|
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0x40100000
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 4616189618054758400
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_neg_4.0_i64:
|
|
; XSI: s_and_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, -4.0
|
|
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 {{s[0-9]+}}, {{s[0-9]+}}, 0xc0100000
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 13839561654909534208
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
|
|
; Test with the 64-bit integer bitpattern for a 32-bit float in the
|
|
; low 32-bits, which is not a valid 64-bit inline immmediate.
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_4.0_i64:
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword s
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 1082130432
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_imm_f32_neg_4.0_i64:
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dwordx2
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, -1065353216
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; Shift into upper 32-bits
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, 4.0
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_high_imm_f32_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 4647714815446351872
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
|
|
; FUNC-LABEL: {{^}}s_and_inline_high_imm_f32_neg_4.0_i64:
|
|
; SI: s_load_dwordx2
|
|
; SI: s_load_dword
|
|
; SI-NOT: and
|
|
; SI: s_and_b32 s[[K_HI:[0-9]+]], s{{[0-9]+}}, -4.0
|
|
; SI-NOT: and
|
|
; SI: buffer_store_dwordx2
|
|
define amdgpu_kernel void @s_and_inline_high_imm_f32_neg_4.0_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %aptr, i64 %a) {
|
|
%and = and i64 %a, 13871086852301127680
|
|
store i64 %and, i64 addrspace(1)* %out, align 8
|
|
ret void
|
|
}
|
|
attributes #0 = { nounwind readnone }
|