mirror of
https://github.com/RPCS3/llvm-mirror.git
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dd292a30dc
Detailed description:
After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.
Discovered issues were addressed in the following commits:
https://reviews.llvm.org/D67662
https://reviews.llvm.org/D67101
https://reviews.llvm.org/D63953
https://reviews.llvm.org/D63731
This change brings back AMDGPU specific changes.
Reviewed by: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
556 lines
16 KiB
LLVM
556 lines
16 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-s-branch-bits=4 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; FIXME: We should use llvm-mc for this, but we can't even parse our own output.
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; See PR33579.
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; RUN: llc -march=amdgcn -verify-machineinstrs -amdgpu-s-branch-bits=4 -o %t.o -filetype=obj %s
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; RUN: llvm-readobj -r %t.o | FileCheck --check-prefix=OBJ %s
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; OBJ: Relocations [
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; OBJ-NEXT: ]
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; Restrict maximum branch to between +7 and -8 dwords
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; Used to emit an always 4 byte instruction. Inline asm always assumes
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; each instruction is the maximum size.
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declare void @llvm.amdgcn.s.sleep(i32) #0
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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; GCN-LABEL: {{^}}uniform_conditional_max_short_forward_branch:
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; GCN: s_load_dword [[CND:s[0-9]+]]
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; GCN: s_cmp_eq_u32 [[CND]], 0
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; GCN-NEXT: s_cbranch_scc1 [[BB3:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: ; %bb.1: ; %bb2
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_sleep 0
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; GCN-NEXT: [[BB3]]: ; %bb3
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; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
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; GCN: buffer_store_dword [[V_CND]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_conditional_max_short_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
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bb:
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%cmp = icmp eq i32 %cnd, 0
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br i1 %cmp, label %bb3, label %bb2 ; +8 dword branch
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bb2:
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; 24 bytes
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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call void @llvm.amdgcn.s.sleep(i32 0)
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br label %bb3
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bb3:
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store volatile i32 %cnd, i32 addrspace(1)* %arg
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ret void
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}
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; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_branch:
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; GCN: s_load_dword [[CND:s[0-9]+]]
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; GCN: s_cmp_eq_u32 [[CND]], 0
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; GCN-NEXT: s_cbranch_scc0 [[LONGBB:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
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; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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; GCN-NEXT: [[LONGBB]]:
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; GCN-NEXT: ;;#ASMSTART
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: [[ENDBB]]:
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; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
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; GCN: buffer_store_dword [[V_CND]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_conditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %cnd) #0 {
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bb0:
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%cmp = icmp eq i32 %cnd, 0
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br i1 %cmp, label %bb3, label %bb2 ; +9 dword branch
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bb2:
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; 32 bytes
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %bb3
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bb3:
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store volatile i32 %cnd, i32 addrspace(1)* %arg
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ret void
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}
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; GCN-LABEL: {{^}}uniform_conditional_min_long_forward_vcnd_branch:
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; GCN: s_load_dword [[CND:s[0-9]+]]
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; GCN-DAG: v_cmp_eq_f32_e64 [[UNMASKED:s\[[0-9]+:[0-9]+\]]], [[CND]], 0
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; GCN-DAG: s_and_b64 vcc, exec, [[UNMASKED]]
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; GCN: s_cbranch_vccz [[LONGBB:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb0
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[ENDBB:BB[0-9]+_[0-9]+]]-([[LONG_JUMP]]+4)
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; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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; GCN-NEXT: [[LONGBB]]:
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: [[ENDBB]]:
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; GCN: v_mov_b32_e32 [[V_CND:v[0-9]+]], [[CND]]
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; GCN: buffer_store_dword [[V_CND]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uniform_conditional_min_long_forward_vcnd_branch(float addrspace(1)* %arg, float %cnd) #0 {
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bb0:
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%cmp = fcmp oeq float %cnd, 0.0
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br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
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bb2:
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call void asm sideeffect " ; 32 bytes
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %bb3
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bb3:
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store volatile float %cnd, float addrspace(1)* %arg
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ret void
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}
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; GCN-LABEL: {{^}}min_long_forward_vbranch:
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; GCN: buffer_load_dword
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; GCN: v_cmp_ne_u32_e32 vcc, 0, v{{[0-9]+}}
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; GCN: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: s_or_b64 exec, exec, [[SAVE]]
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; GCN: buffer_store_dword
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; GCN: s_endpgm
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define amdgpu_kernel void @min_long_forward_vbranch(i32 addrspace(1)* %arg) #0 {
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bb:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = zext i32 %tid to i64
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%gep = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tid.ext
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%load = load volatile i32, i32 addrspace(1)* %gep
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%cmp = icmp eq i32 %load, 0
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br i1 %cmp, label %bb3, label %bb2 ; + 8 dword branch
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bb2:
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call void asm sideeffect " ; 32 bytes
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v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %bb3
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bb3:
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store volatile i32 %load, i32 addrspace(1)* %gep
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ret void
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}
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; GCN-LABEL: {{^}}long_backward_sbranch:
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; GCN: s_mov_b32 [[LOOPIDX:s[0-9]+]], 0{{$}}
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; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]: ; %bb2
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: s_add_i32 [[INC:s[0-9]+]], [[LOOPIDX]], 1
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; GCN-NEXT: s_cmp_lt_i32 [[INC]], 10
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_cbranch_scc0 [[ENDBB:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LONG_JUMP:BB[0-9]+_[0-9]+]]: ; %bb2
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; GCN-NEXT: ; in Loop: Header=[[LOOPBB]] Depth=1
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONG_JUMP]]+4)-[[LOOPBB]]
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; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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; GCN-NEXT: [[ENDBB]]:
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @long_backward_sbranch(i32 addrspace(1)* %arg) #0 {
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bb:
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br label %bb2
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bb2:
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%loop.idx = phi i32 [ 0, %bb ], [ %inc, %bb2 ]
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; 24 bytes
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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%inc = add nsw i32 %loop.idx, 1 ; add cost 4
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%cmp = icmp slt i32 %inc, 10 ; condition cost = 8
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br i1 %cmp, label %bb2, label %bb3 ; -
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bb3:
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ret void
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}
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; Requires expansion of unconditional branch from %bb2 to %bb4 (and
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; expansion of conditional branch from %bb to %bb3.
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; GCN-LABEL: {{^}}uniform_unconditional_min_long_forward_branch:
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; GCN: s_cmp_eq_u32
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; GCN-NEXT: s_cbranch_scc0 [[BB2:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LONG_JUMP0:BB[0-9]+_[0-9]+]]: ; %bb0
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], [[BB3:BB[0-9]_[0-9]+]]-([[LONG_JUMP0]]+4)
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; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], 0{{$}}
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
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; GCN-NEXT: [[BB2]]: ; %bb2
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; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17
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; GCN: buffer_store_dword [[BB2_K]]
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; GCN-NEXT: [[LONG_JUMP1:BB[0-9]+_[0-9]+]]: ; %bb2
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB4:BB[0-9]_[0-9]+]]-([[LONG_JUMP1]]+4)
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; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
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; GCN: [[BB3]]: ; %bb3
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: v_nop_e64
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; GCN: ;;#ASMEND
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; GCN-NEXT: [[BB4]]: ; %bb4
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; GCN: v_mov_b32_e32 [[BB4_K:v[0-9]+]], 63
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; GCN: buffer_store_dword [[BB4_K]]
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; GCN-NEXT: s_endpgm
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; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
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define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
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bb0:
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%tmp = icmp ne i32 %arg1, 0
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br i1 %tmp, label %bb2, label %bb3
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bb2:
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store volatile i32 17, i32 addrspace(1)* undef
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br label %bb4
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bb3:
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; 32 byte asm
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %bb4
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bb4:
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store volatile i32 63, i32 addrspace(1)* %arg
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ret void
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}
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; GCN-LABEL: {{^}}uniform_unconditional_min_long_backward_branch:
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; GCN-NEXT: ; %bb.0: ; %entry
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; GCN-NEXT: [[LOOP:BB[0-9]_[0-9]+]]: ; %loop
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; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
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; GCN-NEXT: ; in Loop: Header=[[LOOP]] Depth=1
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP]]
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; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
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; GCN-NEXT .Lfunc_end{{[0-9]+}}:
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define amdgpu_kernel void @uniform_unconditional_min_long_backward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
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entry:
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br label %loop
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loop:
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; 32 byte asm
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %loop
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}
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; Expansion of branch from %bb1 to %bb3 introduces need to expand
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; branch from %bb0 to %bb2
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; GCN-LABEL: {{^}}expand_requires_expand:
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; GCN-NEXT: ; %bb.0: ; %bb0
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; GCN: s_load_dword
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; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 0{{$}}
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; GCN-NEXT: s_cbranch_scc0 [[BB1:BB[0-9]+_[0-9]+]]
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; GCN-NEXT: [[LONGBB0:BB[0-9]+_[0-9]+]]: ; %bb0
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_add_u32 s[[PC0_LO]], s[[PC0_LO]], [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB0]]+4)
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; GCN-NEXT: s_addc_u32 s[[PC0_HI]], s[[PC0_HI]], 0{{$}}
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC0_LO]]:[[PC0_HI]]{{\]}}
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; GCN-NEXT: [[BB1]]: ; %bb1
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; GCN-NEXT: s_load_dword
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: s_cmp_eq_u32 s{{[0-9]+}}, 3{{$}}
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; GCN-NEXT: s_cbranch_scc0 [[BB2:BB[0-9]_[0-9]+]]
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; GCN-NEXT: [[LONGBB1:BB[0-9]+_[0-9]+]]: ; %bb1
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; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
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; GCN-NEXT: s_add_u32 s[[PC1_LO]], s[[PC1_LO]], [[BB3:BB[0-9]+_[0-9]+]]-([[LONGBB1]]+4)
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; GCN-NEXT: s_addc_u32 s[[PC1_HI]], s[[PC1_HI]], 0{{$}}
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; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC1_LO]]:[[PC1_HI]]{{\]}}
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; GCN-NEXT: [[BB2]]: ; %bb2
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: [[BB3]]: ; %bb3
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: ;;#ASMSTART
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; GCN-NEXT: v_nop_e64
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; GCN-NEXT: ;;#ASMEND
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
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bb0:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
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%cmp0 = icmp slt i32 %cond0, 0
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br i1 %cmp0, label %bb2, label %bb1
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bb1:
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%val = load volatile i32, i32 addrspace(4)* undef
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%cmp1 = icmp eq i32 %val, 3
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br i1 %cmp1, label %bb3, label %bb2
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bb2:
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call void asm sideeffect
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"v_nop_e64
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v_nop_e64
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v_nop_e64
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v_nop_e64", ""() #0
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br label %bb3
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bb3:
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; These NOPs prevent tail-duplication-based outlining
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; from firing, which defeats the need to expand the branches and this test.
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call void asm sideeffect
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"v_nop_e64", ""() #0
|
|
call void asm sideeffect
|
|
"v_nop_e64", ""() #0
|
|
ret void
|
|
}
|
|
|
|
; Requires expanding of required skip branch.
|
|
|
|
; GCN-LABEL: {{^}}uniform_inside_divergent:
|
|
; GCN: v_cmp_gt_u32_e32 vcc, 16, v{{[0-9]+}}
|
|
; GCN-NEXT: s_and_saveexec_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
|
; GCN-NEXT: ; mask branch [[ENDIF:BB[0-9]+_[0-9]+]]
|
|
; GCN-NEXT: s_cbranch_execnz [[IF:BB[0-9]+_[0-9]+]]
|
|
|
|
; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %entry
|
|
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
|
|
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], [[BB2:BB[0-9]_[0-9]+]]-([[LONGBB]]+4)
|
|
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], 0{{$}}
|
|
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
|
|
|
|
; GCN-NEXT: [[IF]]: ; %if
|
|
; GCN: buffer_store_dword
|
|
; GCN: s_cmp_lg_u32
|
|
; GCN: s_cbranch_scc1 [[ENDIF]]
|
|
|
|
; GCN-NEXT: ; %bb.2: ; %if_uniform
|
|
; GCN: buffer_store_dword
|
|
|
|
; GCN-NEXT: [[ENDIF]]: ; %endif
|
|
; GCN-NEXT: s_or_b64 exec, exec, [[MASK]]
|
|
; GCN-NEXT: s_sleep 5
|
|
; GCN-NEXT: s_endpgm
|
|
define amdgpu_kernel void @uniform_inside_divergent(i32 addrspace(1)* %out, i32 %cond) #0 {
|
|
entry:
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%d_cmp = icmp ult i32 %tid, 16
|
|
br i1 %d_cmp, label %if, label %endif
|
|
|
|
if:
|
|
store i32 0, i32 addrspace(1)* %out
|
|
%u_cmp = icmp eq i32 %cond, 0
|
|
br i1 %u_cmp, label %if_uniform, label %endif
|
|
|
|
if_uniform:
|
|
store i32 1, i32 addrspace(1)* %out
|
|
br label %endif
|
|
|
|
endif:
|
|
; layout can remove the split branch if it can copy the return block.
|
|
; This call makes the return block long enough that it doesn't get copied.
|
|
call void @llvm.amdgcn.s.sleep(i32 5);
|
|
ret void
|
|
}
|
|
|
|
; si_mask_branch
|
|
|
|
; GCN-LABEL: {{^}}analyze_mask_branch:
|
|
; GCN: v_cmp_nlt_f32_e32 vcc
|
|
; GCN-NEXT: s_and_saveexec_b64 [[TEMP_MASK:s\[[0-9]+:[0-9]+\]]], vcc
|
|
; GCN-NEXT: s_xor_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[TEMP_MASK]]
|
|
; GCN-NEXT: ; mask branch [[FLOW:BB[0-9]+_[0-9]+]]
|
|
|
|
; GCN: [[FLOW]]: ; %Flow
|
|
; GCN-NEXT: s_or_saveexec_b64 [[TEMP_MASK1:s\[[0-9]+:[0-9]+\]]], [[MASK]]
|
|
; GCN-NEXT: s_xor_b64 exec, exec, [[TEMP_MASK1]]
|
|
; GCN-NEXT: ; mask branch [[RET:BB[0-9]+_[0-9]+]]
|
|
|
|
; GCN: [[LOOP_BODY:BB[0-9]+_[0-9]+]]: ; %loop{{$}}
|
|
; GCN: ;;#ASMSTART
|
|
; GCN: v_nop_e64
|
|
; GCN: v_nop_e64
|
|
; GCN: v_nop_e64
|
|
; GCN: v_nop_e64
|
|
; GCN: v_nop_e64
|
|
; GCN: v_nop_e64
|
|
; GCN: ;;#ASMEND
|
|
; GCN: s_cbranch_vccz [[RET]]
|
|
|
|
; GCN-NEXT: [[LONGBB:BB[0-9]+_[0-9]+]]: ; %loop
|
|
; GCN-NEXT: ; in Loop: Header=[[LOOP_BODY]] Depth=1
|
|
; GCN-NEXT: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
|
|
; GCN-NEXT: s_sub_u32 s[[PC_LO]], s[[PC_LO]], ([[LONGBB]]+4)-[[LOOP_BODY]]
|
|
; GCN-NEXT: s_subb_u32 s[[PC_HI]], s[[PC_HI]], 0
|
|
; GCN-NEXT: s_setpc_b64 s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
|
|
|
|
; GCN-NEXT: [[RET]]: ; %UnifiedReturnBlock
|
|
; GCN-NEXT: s_endpgm
|
|
define amdgpu_kernel void @analyze_mask_branch() #0 {
|
|
entry:
|
|
%reg = call float asm sideeffect "v_mov_b32_e64 $0, 0", "=v"()
|
|
%cmp0 = fcmp ogt float %reg, 0.000000e+00
|
|
br i1 %cmp0, label %loop, label %ret
|
|
|
|
loop:
|
|
%phi = phi float [ 0.000000e+00, %loop_body ], [ 1.000000e+00, %entry ]
|
|
call void asm sideeffect
|
|
"v_nop_e64
|
|
v_nop_e64", ""() #0
|
|
%cmp1 = fcmp olt float %phi, 8.0
|
|
br i1 %cmp1, label %loop_body, label %ret
|
|
|
|
loop_body:
|
|
call void asm sideeffect
|
|
"v_nop_e64
|
|
v_nop_e64
|
|
v_nop_e64
|
|
v_nop_e64", ""() #0
|
|
br label %loop
|
|
|
|
ret:
|
|
store volatile i32 7, i32 addrspace(1)* undef
|
|
ret void
|
|
}
|
|
|
|
; GCN-LABEL: {{^}}long_branch_hang:
|
|
; GCN: s_cmp_lt_i32 s{{[0-9]+}}, 6
|
|
; GCN: s_cbranch_scc1 {{BB[0-9]+_[0-9]+}}
|
|
; GCN-NEXT: s_branch [[LONG_BR_0:BB[0-9]+_[0-9]+]]
|
|
; GCN-NEXT: BB{{[0-9]+_[0-9]+}}:
|
|
|
|
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, [[LONG_BR_DEST0:BB[0-9]+_[0-9]+]]-(
|
|
; GCN-NEXT: s_addc_u32
|
|
; GCN-NEXT: s_setpc_b64
|
|
|
|
; GCN-NEXT: [[LONG_BR_0]]:
|
|
; GCN-DAG: v_cmp_lt_i32
|
|
; GCN-DAG: v_cmp_gt_i32
|
|
; GCN: s_cbranch_vccnz
|
|
|
|
; GCN: s_setpc_b64
|
|
; GCN: s_setpc_b64
|
|
|
|
; GCN: [[LONG_BR_DEST0]]
|
|
; GCN: s_cbranch_vccz
|
|
; GCN: s_setpc_b64
|
|
|
|
; GCN: s_endpgm
|
|
define amdgpu_kernel void @long_branch_hang(i32 addrspace(1)* nocapture %arg, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i64 %arg5) #0 {
|
|
bb:
|
|
%tmp = icmp slt i32 %arg2, 9
|
|
%tmp6 = icmp eq i32 %arg1, 0
|
|
%tmp7 = icmp sgt i32 %arg4, 0
|
|
%tmp8 = icmp sgt i32 %arg4, 5
|
|
br i1 %tmp8, label %bb9, label %bb13
|
|
|
|
bb9: ; preds = %bb
|
|
%tmp10 = and i1 %tmp7, %tmp
|
|
%tmp11 = icmp slt i32 %arg3, %arg4
|
|
%tmp12 = or i1 %tmp11, %tmp7
|
|
br i1 %tmp12, label %bb19, label %bb14
|
|
|
|
bb13: ; preds = %bb
|
|
call void asm sideeffect
|
|
"v_nop_e64
|
|
v_nop_e64
|
|
v_nop_e64
|
|
v_nop_e64", ""() #0
|
|
br i1 %tmp6, label %bb19, label %bb14
|
|
|
|
bb14: ; preds = %bb13, %bb9
|
|
%tmp15 = icmp slt i32 %arg3, %arg4
|
|
%tmp16 = or i1 %tmp15, %tmp
|
|
%tmp17 = and i1 %tmp6, %tmp16
|
|
%tmp18 = zext i1 %tmp17 to i32
|
|
br label %bb19
|
|
|
|
bb19: ; preds = %bb14, %bb13, %bb9
|
|
%tmp20 = phi i32 [ undef, %bb9 ], [ undef, %bb13 ], [ %tmp18, %bb14 ]
|
|
%tmp21 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %arg5
|
|
store i32 %tmp20, i32 addrspace(1)* %tmp21, align 4
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { nounwind }
|
|
attributes #1 = { nounwind readnone }
|