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https://github.com/RPCS3/llvm-mirror.git
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cccd12337a
Before 2018, mesa used to use byval interchangably with inreg, which didn't really make sense. Fix tests still using it to avoid breaking in a future commit. llvm-svn: 365953
117 lines
4.2 KiB
LLVM
117 lines
4.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}test_default_si:
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; GCN: FloatMode: 192
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_default_si(float addrspace(1)* %out0, double addrspace(1)* %out1) #0 {
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store float 0.0, float addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_default_vi:
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; GCN: FloatMode: 192
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_default_vi(float addrspace(1)* %out0, double addrspace(1)* %out1) #1 {
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store float 0.0, float addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f64_denormals:
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; GCN: FloatMode: 192
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #2 {
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store float 0.0, float addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f32_denormals:
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; GCNL: FloatMode: 48
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f32_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #3 {
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store float 0.0, float addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f32_f64_denormals:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f32_f64_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #4 {
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store float 0.0, float addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_no_denormals
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; GCN: FloatMode: 0
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_no_denormals(float addrspace(1)* %out0, double addrspace(1)* %out1) #5 {
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store float 0.0, float addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f16_f64_denormals:
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; GCN: FloatMode: 192
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f16_f64_denormals(half addrspace(1)* %out0, double addrspace(1)* %out1) #6 {
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store half 0.0, half addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_no_f16_f64_denormals:
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; GCN: FloatMode: 0
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_no_f16_f64_denormals(half addrspace(1)* %out0, double addrspace(1)* %out1) #7 {
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store half 0.0, half addrspace(1)* %out0
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store double 0.0, double addrspace(1)* %out1
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ret void
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}
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; GCN-LABEL: {{^}}test_f32_f16_f64_denormals:
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; GCN: FloatMode: 240
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; GCN: IeeeMode: 1
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define amdgpu_kernel void @test_f32_f16_f64_denormals(half addrspace(1)* %out0, float addrspace(1)* %out1, double addrspace(1)* %out2) #8 {
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store half 0.0, half addrspace(1)* %out0
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store float 0.0, float addrspace(1)* %out1
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store double 0.0, double addrspace(1)* %out2
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ret void
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}
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; GCN-LABEL: {{^}}kill_gs_const:
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; GCN: IeeeMode: 0
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define amdgpu_gs void @kill_gs_const() {
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main_body:
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%cmp0 = icmp ule i32 0, 3
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call void @llvm.amdgcn.kill(i1 %cmp0)
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%cmp1 = icmp ule i32 3, 0
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call void @llvm.amdgcn.kill(i1 %cmp1)
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ret void
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}
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; GCN-LABEL: {{^}}kill_vcc_implicit_def:
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; GCN: IeeeMode: 0
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define amdgpu_ps float @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(4)* inreg, [17 x <16 x i8>] addrspace(4)* inreg, [17 x <4 x i32>] addrspace(4)* inreg, [34 x <8 x i32>] addrspace(4)* inreg, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
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entry:
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%tmp0 = fcmp olt float %13, 0.0
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call void @llvm.amdgcn.kill(i1 %tmp0)
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%tmp1 = select i1 %tmp0, float 1.0, float 0.0
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ret float %tmp1
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}
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declare void @llvm.amdgcn.kill(i1)
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attributes #0 = { nounwind "target-cpu"="tahiti" }
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attributes #1 = { nounwind "target-cpu"="fiji" }
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attributes #2 = { nounwind "target-features"="+fp64-denormals" }
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attributes #3 = { nounwind "target-features"="+fp32-denormals" }
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attributes #4 = { nounwind "target-features"="+fp32-denormals,+fp64-denormals" }
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attributes #5 = { nounwind "target-features"="-fp32-denormals,-fp64-fp16-denormals" }
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attributes #6 = { nounwind "target-features"="+fp64-fp16-denormals" }
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attributes #7 = { nounwind "target-features"="-fp64-fp16-denormals" }
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attributes #8 = { nounwind "target-features"="+fp32-denormals,+fp64-fp16-denormals" }
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