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4762eb1825
The adc/sbb optimization is to able to convert following expression into a single adc/sbb instruction: (ult) ... = x + 1 // where the ult is unsigned-less-than comparison (ult) ... = x - 1 This change is to flip the "x >u y" (i.e. ugt comparison) in order to expose the adc/sbb opportunity. llvm-svn: 167180
47 lines
1.1 KiB
LLVM
47 lines
1.1 KiB
LLVM
; RUN: llc < %s -march=x86 | FileCheck %s
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; <rdar://problem/8449754>
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define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
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entry:
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; CHECK: test1:
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; CHECK: cmpl %ecx, %eax
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; CHECK-NOT: addl
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; CHECK: adcl $0, %eax
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%add4 = add i32 %x, %sum
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%cmp = icmp ult i32 %add4, %x
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%inc = zext i1 %cmp to i32
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%z.0 = add i32 %add4, %inc
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ret i32 %z.0
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}
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; Instcombine transforms test1 into test2:
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; CHECK: test2:
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; CHECK: movl
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; CHECK-NEXT: addl
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; CHECK-NEXT: adcl $0
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; CHECK-NEXT: ret
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define i32 @test2(i32 %sum, i32 %x) nounwind readnone ssp {
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entry:
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %x, i32 %sum)
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%0 = extractvalue { i32, i1 } %uadd, 0
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%cmp = extractvalue { i32, i1 } %uadd, 1
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%inc = zext i1 %cmp to i32
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%z.0 = add i32 %0, %inc
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ret i32 %z.0
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}
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; <rdar://problem/12579915>
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define i32 @test3(i32 %x, i32 %y, i32 %res) nounwind uwtable readnone ssp {
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entry:
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%cmp = icmp ugt i32 %x, %y
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%dec = sext i1 %cmp to i32
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%dec.res = add nsw i32 %dec, %res
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ret i32 %dec.res
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; CHECK: test3:
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; CHECK: cmpl
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; CHECK: sbbl
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; CHECK: ret
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}
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
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