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llvm-mirror/test/CodeGen/ARM/2011-09-28-CMovCombineBug.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

31 lines
727 B
LLVM

; RUN: llc -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 < %s
; rdar://10196296
; ARM target specific dag combine created a cycle in DAG.
define void @t() nounwind ssp {
%1 = load i64, i64* undef, align 4
%2 = shl i32 5, 0
%3 = zext i32 %2 to i64
%4 = and i64 %1, %3
%5 = lshr i64 %4, undef
switch i64 %5, label %8 [
i64 0, label %9
i64 1, label %6
i64 4, label %9
i64 5, label %7
]
; <label>:6 ; preds = %0
unreachable
; <label>:7 ; preds = %0
unreachable
; <label>:8 ; preds = %0
unreachable
; <label>:9 ; preds = %0, %0
ret void
}