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e835f56682
v2: Add test (Matt). Fix capitalization of isEOP (Matt). Move pattern to class parameter (Matt). Make the instruction available to Cayman (Matt). Change name from MEM_RAT WRITE_TYPED to MEM_RAT STORE_TYPED. Patch by: Zoltan Gilian llvm-svn: 249042
131 lines
4.6 KiB
TableGen
131 lines
4.6 KiB
TableGen
//===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the R600-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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let TargetPrefix = "r600" in {
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class R600ReadPreloadRegisterIntrinsic<string name>
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<name>;
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multiclass R600ReadPreloadRegisterIntrinsic_xyz<string prefix> {
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def _x : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_x")>;
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def _y : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_y")>;
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def _z : R600ReadPreloadRegisterIntrinsic<!strconcat(prefix, "_z")>;
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}
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defm int_r600_read_global_size : R600ReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_global_size">;
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defm int_r600_read_local_size : R600ReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_local_size">;
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defm int_r600_read_ngroups : R600ReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_ngroups">;
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defm int_r600_read_tgid : R600ReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_tgid">;
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defm int_r600_read_tidig : R600ReadPreloadRegisterIntrinsic_xyz <
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"__builtin_r600_read_tidig">;
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def int_r600_rat_store_typed :
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// 1st parameter: Data
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// 2nd parameter: Index
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// 3rd parameter: Constant RAT ID
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Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
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GCCBuiltin<"__builtin_r600_rat_store_typed">;
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} // End TargetPrefix = "r600"
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let TargetPrefix = "AMDGPU" in {
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class AMDGPUReadPreloadRegisterIntrinsic<string name>
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>,
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GCCBuiltin<name>;
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def int_AMDGPU_div_scale : GCCBuiltin<"__builtin_amdgpu_div_scale">,
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// 1st parameter: Numerator
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// 2nd parameter: Denominator
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// 3rd parameter: Constant to select select between first and
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// second. (0 = first, 1 = second).
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Intrinsic<[llvm_anyfloat_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
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[IntrNoMem]>;
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def int_AMDGPU_div_fmas : GCCBuiltin<"__builtin_amdgpu_div_fmas">,
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Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
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[IntrNoMem]>;
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def int_AMDGPU_div_fixup : GCCBuiltin<"__builtin_amdgpu_div_fixup">,
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Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]>;
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def int_AMDGPU_trig_preop : GCCBuiltin<"__builtin_amdgpu_trig_preop">,
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty],
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[IntrNoMem]>;
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def int_AMDGPU_rcp : GCCBuiltin<"__builtin_amdgpu_rcp">,
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_AMDGPU_rsq : GCCBuiltin<"__builtin_amdgpu_rsq">,
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_AMDGPU_rsq_clamped : GCCBuiltin<"__builtin_amdgpu_rsq_clamped">,
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_AMDGPU_ldexp : GCCBuiltin<"__builtin_amdgpu_ldexp">,
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Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_class : GCCBuiltin<"__builtin_amdgpu_class">,
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Intrinsic<[llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_AMDGPU_read_workdim : AMDGPUReadPreloadRegisterIntrinsic <
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"__builtin_amdgpu_read_workdim">;
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} // End TargetPrefix = "AMDGPU"
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let TargetPrefix = "amdgcn" in {
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// SI only
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def int_amdgcn_buffer_wbinvl1_sc :
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GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">,
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Intrinsic<[], [], []>;
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// On CI+
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def int_amdgcn_buffer_wbinvl1_vol :
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GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">,
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Intrinsic<[], [], []>;
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def int_amdgcn_buffer_wbinvl1 :
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GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">,
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Intrinsic<[], [], []>;
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def int_amdgcn_s_dcache_inv :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">,
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Intrinsic<[], [], []>;
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// CI+
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def int_amdgcn_s_dcache_inv_vol :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">,
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Intrinsic<[], [], []>;
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// VI
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def int_amdgcn_s_dcache_wb :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">,
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Intrinsic<[], [], []>;
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// VI
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def int_amdgcn_s_dcache_wb_vol :
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GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">,
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Intrinsic<[], [], []>;
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}
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