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07d39af714
Implement getRegPressureLimit and getRegPressureSetLimit callbacks in SIRegisterInfo. This makes standard converge scheduler to behave almost the same as GCNScheduler, sometime slightly better sometimes a bit worse. In gerenal that is also possible to switch GCNScheduler to use these callbacks instead of getMaxWaves(), which also makes GCNScheduler slightly better on some tests and slightly worse on another. A big win is behavior with converge scheduler. Note, these are used not only by scheduling, but in places like MachineLICM. Differential Revision: https://reviews.llvm.org/D29700 llvm-svn: 294518
230 lines
8.4 KiB
C++
230 lines
8.4 KiB
C++
//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for SIRegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
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#include "AMDGPURegisterInfo.h"
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#include "SIDefines.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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namespace llvm {
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class SISubtarget;
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class MachineRegisterInfo;
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class SIMachineFunctionInfo;
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class SIRegisterInfo final : public AMDGPURegisterInfo {
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private:
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unsigned SGPRSetID;
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unsigned VGPRSetID;
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BitVector SGPRPressureSets;
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BitVector VGPRPressureSets;
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void reserveRegisterTuples(BitVector &, unsigned Reg) const;
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void classifyPressureSet(unsigned PSetID, unsigned Reg,
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BitVector &PressureSets) const;
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public:
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SIRegisterInfo();
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/// Return the end register initially reserved for the scratch buffer in case
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/// spilling is needed.
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unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
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/// Return the end register initially reserved for the scratch wave offset in
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/// case spilling is needed.
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unsigned reservedPrivateSegmentWaveByteOffsetReg(
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const MachineFunction &MF) const;
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
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bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
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bool requiresFrameIndexReplacementScavenging(
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const MachineFunction &MF) const override;
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bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
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bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
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int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
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int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
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int Idx) const override;
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bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
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void materializeFrameBaseRegister(MachineBasicBlock *MBB,
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unsigned BaseReg, int FrameIdx,
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int64_t Offset) const override;
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void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
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int64_t Offset) const override;
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bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
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int64_t Offset) const override;
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const TargetRegisterClass *getPointerRegClass(
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const MachineFunction &MF, unsigned Kind = 0) const override;
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void spillSGPR(MachineBasicBlock::iterator MI,
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int FI, RegScavenger *RS) const;
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void restoreSGPR(MachineBasicBlock::iterator MI,
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int FI, RegScavenger *RS) const;
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void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const override;
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unsigned getHWRegIndex(unsigned Reg) const {
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return getEncodingValue(Reg) & 0xff;
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}
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/// \brief Return the 'base' register class for this register.
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/// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
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const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
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/// \returns true if this class contains only SGPR registers
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bool isSGPRClass(const TargetRegisterClass *RC) const {
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return !hasVGPRs(RC);
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}
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/// \returns true if this class ID contains only SGPR registers
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bool isSGPRClassID(unsigned RCID) const {
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return isSGPRClass(getRegClass(RCID));
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}
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bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
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const TargetRegisterClass *RC;
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if (TargetRegisterInfo::isVirtualRegister(Reg))
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RC = MRI.getRegClass(Reg);
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else
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RC = getPhysRegClass(Reg);
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return isSGPRClass(RC);
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}
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/// \returns true if this class contains VGPR registers.
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bool hasVGPRs(const TargetRegisterClass *RC) const;
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/// \returns A VGPR reg class with the same width as \p SRC
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const TargetRegisterClass *getEquivalentVGPRClass(
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const TargetRegisterClass *SRC) const;
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/// \returns A SGPR reg class with the same width as \p SRC
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const TargetRegisterClass *getEquivalentSGPRClass(
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const TargetRegisterClass *VRC) const;
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/// \returns The register class that is used for a sub-register of \p RC for
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/// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
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/// be returned.
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const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
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unsigned SubIdx) const;
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bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
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unsigned DefSubReg,
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const TargetRegisterClass *SrcRC,
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unsigned SrcSubReg) const override;
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/// \returns True if operands defined with this operand type can accept
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/// a literal constant (i.e. any 32-bit immediate).
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bool opCanUseLiteralConstant(unsigned OpType) const {
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// TODO: 64-bit operands have extending behavior from 32-bit literal.
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return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
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OpType <= AMDGPU::OPERAND_REG_IMM_LAST;
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}
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/// \returns True if operands defined with this operand type can accept
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/// an inline constant. i.e. An integer value in the range (-16, 64) or
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/// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
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bool opCanUseInlineConstant(unsigned OpType) const {
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return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
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OpType <= AMDGPU::OPERAND_SRC_LAST;
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}
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enum PreloadedValue {
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// SGPRS:
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PRIVATE_SEGMENT_BUFFER = 0,
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DISPATCH_PTR = 1,
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QUEUE_PTR = 2,
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KERNARG_SEGMENT_PTR = 3,
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DISPATCH_ID = 4,
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FLAT_SCRATCH_INIT = 5,
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WORKGROUP_ID_X = 10,
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WORKGROUP_ID_Y = 11,
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WORKGROUP_ID_Z = 12,
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PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
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// VGPRS:
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FIRST_VGPR_VALUE = 15,
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WORKITEM_ID_X = FIRST_VGPR_VALUE,
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WORKITEM_ID_Y = 16,
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WORKITEM_ID_Z = 17
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};
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/// \brief Returns the physical register that \p Value is stored in.
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unsigned getPreloadedValue(const MachineFunction &MF,
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enum PreloadedValue Value) const;
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unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
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const TargetRegisterClass *RC,
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const MachineFunction &MF) const;
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unsigned getSGPRPressureSet() const { return SGPRSetID; };
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unsigned getVGPRPressureSet() const { return VGPRSetID; };
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const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
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unsigned Reg) const;
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bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
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bool isSGPRPressureSet(unsigned SetID) const {
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return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
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}
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bool isVGPRPressureSet(unsigned SetID) const {
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return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
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}
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ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
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unsigned EltSize) const;
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bool shouldCoalesce(MachineInstr *MI,
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const TargetRegisterClass *SrcRC,
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unsigned SubReg,
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const TargetRegisterClass *DstRC,
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unsigned DstSubReg,
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const TargetRegisterClass *NewRC) const override;
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unsigned getRegPressureLimit(const TargetRegisterClass *RC,
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MachineFunction &MF) const override;
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unsigned getRegPressureSetLimit(const MachineFunction &MF,
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unsigned Idx) const override;
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private:
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void buildSpillLoadStore(MachineBasicBlock::iterator MI,
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unsigned LoadStoreOp,
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int Index,
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unsigned ValueReg,
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bool ValueIsKill,
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unsigned ScratchRsrcReg,
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unsigned ScratchOffsetReg,
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int64_t InstrOffset,
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MachineMemOperand *MMO,
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RegScavenger *RS) const;
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};
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} // End namespace llvm
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#endif
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