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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 19:23:23 +01:00
llvm-mirror/test/CodeGen
Akira Hatanaka 76bd57e472 [ARM] Pass a callback to FunctionPass constructors to enable skipping execution
on a per-function basis.

Previously some of the passes were conditionally added to ARM's pass pipeline
based on the target machine's subtarget. This patch makes changes to add those
passes unconditionally and execute them conditonally based on the predicate
functor passed to the pass constructors. This enables running different sets of
passes for different functions in the module.

rdar://problem/20542263

Differential Revision: http://reviews.llvm.org/D8717

llvm-svn: 239325
2015-06-08 18:50:43 +00:00
..
AArch64 [GlobalMerge] Take into account minsize on Global users' parents. 2015-06-04 20:39:23 +00:00
ARM [ARM] Pass a callback to FunctionPass constructors to enable skipping execution 2015-06-08 18:50:43 +00:00
BPF [bpf] rename triple names bpf_be -> bpfeb 2015-06-05 16:11:14 +00:00
CPP
Generic
Hexagon [Hexagon] Adding functionality for searching for compound instruction pairs. Compound instructions reduce slot resource requirements freeing those packet slots up for more instructions. 2015-06-08 16:34:47 +00:00
Inputs
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR
MSP430
NVPTX [NVPTX] roll forward r239082 2015-06-04 21:28:26 +00:00
PowerPC
R600 DAGCombiner: don't duplicate (fmul x, c) in visitFNEG if fneg is free 2015-06-05 17:52:34 +00:00
SPARC
SystemZ
Thumb Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM." 2015-06-05 18:01:28 +00:00
Thumb2 ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
WinEH
X86 X86: Reject register operands with obvious type mismatches. 2015-06-08 16:56:23 +00:00
XCore