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4e1d2d8ecf
Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D34589 llvm-svn: 306298
89 lines
2.8 KiB
C++
89 lines
2.8 KiB
C++
//===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for
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/// AMDGPU.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "AMDGPULegalizerInfo.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Target/TargetOpcodes.h"
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using namespace llvm;
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#ifndef LLVM_BUILD_GLOBAL_ISEL
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#error "You shouldn't build this"
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#endif
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AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
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using namespace TargetOpcode;
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const LLT S1= LLT::scalar(1);
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const LLT V2S16 = LLT::vector(2, 16);
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const LLT S32 = LLT::scalar(32);
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const LLT S64 = LLT::scalar(64);
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const LLT P1 = LLT::pointer(1, 64);
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const LLT P2 = LLT::pointer(2, 64);
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setAction({G_ADD, S32}, Legal);
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setAction({G_AND, S32}, Legal);
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setAction({G_BITCAST, V2S16}, Legal);
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setAction({G_BITCAST, 1, S32}, Legal);
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setAction({G_BITCAST, S32}, Legal);
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setAction({G_BITCAST, 1, V2S16}, Legal);
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// FIXME: i1 operands to intrinsics should always be legal, but other i1
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// values may not be legal. We need to figure out how to distinguish
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// between these two scenarios.
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setAction({G_CONSTANT, S1}, Legal);
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setAction({G_CONSTANT, S32}, Legal);
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setAction({G_CONSTANT, S64}, Legal);
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setAction({G_FCONSTANT, S32}, Legal);
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setAction({G_GEP, P1}, Legal);
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setAction({G_GEP, P2}, Legal);
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setAction({G_GEP, 1, S64}, Legal);
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setAction({G_ICMP, S1}, Legal);
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setAction({G_ICMP, 1, S32}, Legal);
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setAction({G_LOAD, P1}, Legal);
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setAction({G_LOAD, P2}, Legal);
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setAction({G_LOAD, S32}, Legal);
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setAction({G_LOAD, 1, P1}, Legal);
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setAction({G_LOAD, 1, P2}, Legal);
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setAction({G_SELECT, S32}, Legal);
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setAction({G_SELECT, 1, S1}, Legal);
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setAction({G_SHL, S32}, Legal);
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setAction({G_STORE, S32}, Legal);
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setAction({G_STORE, 1, P1}, Legal);
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// FIXME: When RegBankSelect inserts copies, it will only create new
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// registers with scalar types. This means we can end up with
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// G_LOAD/G_STORE/G_GEP instruction with scalar types for their pointer
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// operands. In assert builds, the instruction selector will assert
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// if it sees a generic instruction which isn't legal, so we need to
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// tell it that scalar types are legal for pointer operands
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setAction({G_GEP, S64}, Legal);
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setAction({G_LOAD, 1, S64}, Legal);
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setAction({G_STORE, 1, S64}, Legal);
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computeTables();
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}
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