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d615e606c4
Before:
adr r12, #LJTI3_0_0
ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
.long LBB3_24
.long LBB3_30
.long LBB3_31
.long LBB3_32
After:
adr r12, #LJTI3_0_0
add pc, r12, +r0, lsl #2
LJTI3_0_0:
b.w LBB3_24
b.w LBB3_30
b.w LBB3_31
b.w LBB3_32
This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
(smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
won't have to over-estimate the size.
Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.
llvm-svn: 77024
12 lines
579 B
Plaintext
12 lines
579 B
Plaintext
//===---------------------------------------------------------------------===//
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// Random ideas for the ARM backend (Thumb2 specific).
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//===---------------------------------------------------------------------===//
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* We should model IT instructions explicitly. We should introduce them (even if
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if-converter is not run, the function could still contain movcc's) before
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PEI since passes starting from PEI may require exact code size.
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//===---------------------------------------------------------------------===//
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Make use of TBB and TBH for jumptables in small functions.
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