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efe6e9b9fb
Summary:
[Thumb] set code alignment for 16-bit load from constant pool
LLVM miscompiles this code when compiling for a target with v8.2-A FP16 and the Thumb ISA at -O0:
extern void bar(__fp16 P5);
int main() {
__fp16 P5 = 1.96875;
bar(P5);
}
The code section containing main has 2 byte alignment.
It needs to have 4 byte alignment,
because the load literal instruction has an offset from the
load address with the low 2 bits zeroed.
I do not include a test case in this check-in.
llc and llvm-mc do not exhibit this bug. They do not set code section alignment
in the same manner as clang.
Reviewers: dnsampaio
Reviewed By: dnsampaio
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D84169
60 lines
2.1 KiB
YAML
60 lines
2.1 KiB
YAML
# RUN: llc -mtriple=arm-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8.2a-arm-none-eabi"
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define hidden i32 @main() {
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entry:
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%P5 = alloca half, align 2
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store half 0xH3FE0, half* %P5, align 2
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%0 = load half, half* %P5, align 2
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call void @z_bar(half %0)
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ret i32 0
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}
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declare dso_local void @z_bar(half)
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...
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---
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name: main
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alignment: 2
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tracksRegLiveness: true
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frameInfo:
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stackSize: 16
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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localFrameSize: 2
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stack:
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- { id: 0, name: P5, offset: -10, size: 2, alignment: 2, local-offset: -2 }
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- { id: 1, type: spill-slot, offset: -4, size: 4, alignment: 4, callee-saved-register: '$lr',
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callee-saved-restored: false }
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- { id: 2, type: spill-slot, offset: -8, size: 4, alignment: 4, callee-saved-register: '$r7' }
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constants:
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- id: 0
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value: half 0xH3FE0
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alignment: 2
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $r7, $lr
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frame-setup tPUSH 14 /* CC::al */, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
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frame-setup CFI_INSTRUCTION def_cfa_offset 8
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frame-setup CFI_INSTRUCTION offset $lr, -4
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frame-setup CFI_INSTRUCTION offset $r7, -8
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$sp = frame-setup tSUBspi $sp, 2, 14 /* CC::al */, $noreg
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frame-setup CFI_INSTRUCTION def_cfa_offset 16
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renamable $s0 = VLDRH %const.0, 0, 14, $noreg :: (load 2 from constant-pool)
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VSTRH killed renamable $s0, $sp, 3, 14, $noreg :: (store 2 into %ir.P5)
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renamable $r0 = t2LDRHi12 $sp, 6, 14 /* CC::al */, $noreg :: (dereferenceable load 2 from %ir.P5)
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tBL 14 /* CC::al */, $noreg, @z_bar, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp
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renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
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$sp = frame-destroy tADDspi $sp, 2, 14 /* CC::al */, $noreg
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frame-destroy tPOP_RET 14 /* CC::al */, $noreg, def $r7, def $pc, implicit killed $r0
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; CHECK: name: main
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; CHECK-NEXT: alignment: 4
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...
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