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925690f23e
BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
82 lines
1.7 KiB
LLVM
82 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
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; RUN: | FileCheck %s
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; rdar://7461510
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; rdar://10964603
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; Disable this optimization unless we know one of them is zero.
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define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
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entry:
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; CHECK-LABEL: t1:
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; CHECK: vldr [[S0:s[0-9]+]],
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; CHECK: vldr [[S1:s[0-9]+]],
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; CHECK: vcmp.f32 [[S1]], [[S0]]
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; CHECK: vmrs APSR_nzcv, fpscr
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; CHECK: beq
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%0 = load float, float* %a
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%1 = load float, float* %b
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%2 = fcmp une float %0, %1
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br i1 %2, label %bb1, label %bb2
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bb1:
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%3 = call i32 @bar()
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ret i32 %3
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bb2:
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%4 = call i32 @foo()
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ret i32 %4
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}
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; If one side is zero, the other size sign bit is masked off to allow
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; +0.0 == -0.0
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define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
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entry:
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; CHECK-LABEL: t2:
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; CHECK-NOT: vldr
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; CHECK: ldrd [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], [r0]
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; CHECK-NOT: b LBB
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; CHECK: bic [[REG2]], [[REG2]], #-2147483648
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; CHECK: cmp [[REG1]], #0
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; CHECK: cmpeq [[REG2]], #0
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; CHECK-NOT: vcmp.f32
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; CHECK-NOT: vmrs
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; CHECK: bne
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%0 = load double, double* %a
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%1 = fcmp oeq double %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
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bb1:
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%2 = call i32 @bar()
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ret i32 %2
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bb2:
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%3 = call i32 @foo()
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ret i32 %3
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}
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define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
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entry:
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; CHECK-LABEL: t3:
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; CHECK-NOT: vldr
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; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
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; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
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; CHECK: tst [[REG3]], [[REG4]]
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; CHECK-NOT: vcmp.f32
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; CHECK-NOT: vmrs
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; CHECK: bne
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%0 = load float, float* %a
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%1 = fcmp oeq float %0, 0.000000e+00
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br i1 %1, label %bb1, label %bb2
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bb1:
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%2 = call i32 @bar()
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ret i32 %2
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bb2:
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%3 = call i32 @foo()
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ret i32 %3
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}
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declare i32 @bar()
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declare i32 @foo()
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