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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/test/CodeGen/NVPTX
Sven van Haastregt a77c70490e [TargetLowering] Add i1 condition for bit comparison fold
For i1 types, boolean false is represented identically regardless of
the boolean content, so we can allow optimizations that otherwise
would not be correct for booleans with false represented as a negative
one.

Patch by Erik Hogeman.

Differential Revision: https://reviews.llvm.org/D90145
2020-10-27 12:22:20 +00:00
..
access-non-generic.ll
add-128bit.ll
addrspacecast-gvar.ll
addrspacecast.ll
aggr-param.ll
aggregate-return.ll
alias.ll
annotations.ll
arg-lowering.ll
arithmetic-fp-sm20.ll
arithmetic-int.ll
atomics-sm60.ll
atomics-with-scope.ll
atomics.ll
barrier.ll
bfe.ll
branch-fold.ll
bug17709.ll
bug21465.ll
bug22246.ll
bug22322.ll
bug26185-2.ll
bug26185.ll
bug41651.ll
bypass-div.ll
call-with-alloca-buffer.ll
callchain.ll
calling-conv.ll
calls-with-phi.ll
combine-min-max.ll
compare-int.ll
constant-vectors.ll
convergent-mir-call.ll
convert-fp.ll
convert-int-sm20.ll
ctlz.ll
ctpop.ll
cttz.ll
disable-opt.ll
div-ri.ll
divrem-combine.ll
envreg.ll
extloadv.ll
f16-instructions.ll
f16x2-instructions.ll
fast-math.ll
fcos-no-fast-math.ll
fma-assoc.ll
fma-disable.ll
fma.ll
fns.ll
fp16.ll
fp-contract.ll
fp-literals.ll
fsin-no-fast-math.ll
function-align.ll
generic-to-nvvm-ir.ll
generic-to-nvvm.ll
global-addrspace.ll
global-ctor-empty.ll
global-ctor.ll
global-dtor.ll
global-ordering.ll
global-variable-big.ll
global-visibility.ll
globals_init.ll
globals_lowering.ll
gvar-init.ll
half.ll
i1-global.ll
i1-int-to-fp.ll
i1-param.ll
i8-param.ll
i128-global.ll
i128-param.ll
i128-retval.ll
i128-struct.ll
idioms.ll
imad.ll
inline-asm.ll
inlineasm-output-template.ll
intrin-nocapture.ll
intrinsic-old.ll
intrinsics.ll
isspacep.ll
ld-addrspace.ll
ld-generic.ll
ld-st-addrrspace.py
ldg-invariant.ll
ldparam-v4.ll
ldu-i8.ll
ldu-ldg.ll
ldu-reg-plus-offset.ll
libcall-fulfilled.ll
libcall-instruction.ll
libcall-intrinsic.ll
lit.local.cfg
load-sext-i1.ll
load-store.ll
load-with-non-coherent-cache.ll
LoadStoreVectorizer.ll
local-stack-frame.ll
loop-vectorize.ll
lower-aggr-copies.ll
lower-alloca.ll
lower-args.ll Preserve param alignment in NVPTXLowerArgs pass. 2020-10-14 11:15:30 -07:00
lower-kernel-ptr-arg.ll
machine-sink.ll
MachineSink-call.ll
MachineSink-convergent.ll
managed.ll
match.ll
math-intrins.ll
minmax-negative.ll
misaligned-vector-ldst.ll
module-inline-asm.ll
mulwide.ll
named-barriers.ll
noduplicate-syncthreads.ll
nofunc.ll
nounroll.ll
nvcl-param-align.ll
nvvm-reflect-arch.ll
nvvm-reflect-module-flag.ll
nvvm-reflect.ll
param-align.ll
param-load-store.ll
pow2_mask_cmp.ll [TargetLowering] Add i1 condition for bit comparison fold 2020-10-27 12:22:20 +00:00
pr13291-i1-store.ll
pr16278.ll
pr17529.ll
proxy-reg-erasure-mir.ll
proxy-reg-erasure-ptx.ll
read-global-variable-constant.ll
refl1.ll
reg-copy.ll
reg-types.ll
rotate.ll
sched1.ll
sched2.ll
sext-in-reg.ll
sext-params.ll
shfl-p.ll
shfl-sync-p.ll
shfl-sync.ll
shfl.ll
shift-parts.ll
simple-call.ll
sm-version-20.ll
sm-version-21.ll
sm-version-30.ll
sm-version-32.ll
sm-version-35.ll
sm-version-37.ll
sm-version-50.ll
sm-version-52.ll
sm-version-53.ll
sm-version-60.ll
sm-version-61.ll
sm-version-62.ll
sm-version-70.ll
speculative-execution-divergent-target.ll
sqrt-approx.ll
st-addrspace.ll
st-generic.ll
surf-read-cuda.ll
surf-read.ll
surf-write-cuda.ll
surf-write.ll
symbol-naming.ll
TailDuplication-convergent.ll
tex-read-cuda.ll
tex-read.ll
texsurf-queries.ll
tid-range.ll
tuple-literal.ll
vec8.ll
vec-param-load.ll
vector-args.ll
vector-call.ll
vector-compare.ll
vector-global.ll
vector-loads.ll
vector-select.ll
vector-stores.ll
vectorize-misaligned.ll
vote.ll
weak-global.ll
weak-linkage.ll
wmma.py
zeroext-32bit.ll