Craig Topper 3773c0093a [RISCV] When matching SROIW, check all 64 bits of the OR mask ... We need to make sure the upper 32 bits are all ones to ensure the result is properly sign extended. Previously we only checked the lower 32 bits of the mask. I've also added a check that the shift amount is less than 32. Without that the original code asserts inside maskLeadingOnes if the SROI check is removed or the SROIW pattern is checked first. I've refactored the code to use early outs to reduce nesting. I've also updated SLOIW matching with the same changes, but I couldn't find a broken test case with the existing code. Differential Revision: https://reviews.llvm.org/D90961		2020-11-16 10:08:15 -08:00
..
GlobalISel
intrinsics
add-before-shl.ll
add-imm.ll
addc-adde-sube-subc.ll
addcarry.ll
addimm-mulimm.ll
align.ll
alloca.ll
alu8.ll
alu16.ll
alu32.ll
alu64.ll
analyze-branch.ll
arith-with-overflow.ll
atomic-cmpxchg-flag.ll
atomic-cmpxchg.ll
atomic-fence.ll
atomic-load-store.ll
atomic-rmw.ll
attributes.ll
bare-select.ll
blockaddress.ll
branch-relaxation.ll
branch.ll
bswap-ctlz-cttz-ctpop.ll
byval.ll
callee-saved-fpr32s.ll
callee-saved-fpr64s.ll
callee-saved-gprs.ll
calling-conv-ilp32-ilp32f-common.ll
calling-conv-ilp32-ilp32f-ilp32d-common.ll
calling-conv-ilp32.ll
calling-conv-ilp32d.ll
calling-conv-ilp32f-ilp32d-common.ll
calling-conv-lp64-lp64f-common.ll
calling-conv-lp64-lp64f-lp64d-common.ll
calling-conv-lp64.ll
calling-conv-rv32f-ilp32.ll
calling-conv-sext-zext.ll
calls.ll
cmp-bool.ll
codemodel-lowering.ll
compress-float.ll
compress-inline-asm.ll
compress.ll
copy-frameindex.mir	[RISCV] Only return DestSourcePair from isCopyInstrImpl for registers	2020-11-03 03:55:47 +00:00
copysign-casts.ll
disable-tail-calls.ll
disjoint.ll
div.ll
double-arith.ll	[RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand instead of the first.	2020-11-05 14:00:25 -08:00
double-bitmanip-dagcombines.ll
double-br-fcmp.ll
double-calling-conv.ll
double-convert.ll
double-fcmp.ll
double-frem.ll
double-imm.ll
double-intrinsics.ll
double-isnan.ll
double-mem.ll
double-previous-failure.ll
double-select-fcmp.ll
double-stack-spill-restore.ll
dwarf-eh.ll
exception-pointer-register.ll
fastcc-float.ll
fastcc-int.ll
fixups-diff.ll
fixups-relax-diff.ll
float-arith.ll	[RISCV] Add isel patterns for fnmadd/fnmsub with an fneg on the second operand instead of the first.	2020-11-05 14:00:25 -08:00
float-bit-preserving-dagcombines.ll
float-bitmanip-dagcombines.ll
float-br-fcmp.ll
float-convert.ll
float-fcmp.ll
float-frem.ll
float-imm.ll
float-intrinsics.ll
float-isnan.ll
float-mem.ll
float-select-fcmp.ll
flt-rounds.ll
fold-addi-loadstore.ll
fp16-promote.ll
fp128.ll
fp-imm.ll
frame-info.ll
frame.ll
frameaddr-returnaddr.ll
get-register-invalid.ll
get-register-noreserve.ll
get-register-reserve.ll
get-setcc-result-type.ll
hoist-global-addr-base.ll
i32-icmp.ll
imm-cse.ll
imm.ll	[RISCV][NFC] Add more tests for 32-bit constant materialization	2020-10-22 11:36:34 +01:00
indirectbr.ll
init-array.ll
inline-asm-abi-names.ll
inline-asm-clobbers.ll
inline-asm-d-abi-names.ll
inline-asm-d-constraint-f.ll
inline-asm-f-abi-names.ll
inline-asm-f-constraint-f.ll
inline-asm-i-constraint-i1.ll
inline-asm-invalid.ll
inline-asm.ll
interrupt-attr-args-error.ll
interrupt-attr-callee.ll
interrupt-attr-invalid.ll
interrupt-attr-nocall.ll
interrupt-attr-ret-error.ll
interrupt-attr.ll
jumptable.ll
large-stack.ll
legalize-fneg.ll
lit.local.cfg
lsr-legaladdimm.ll
machineoutliner.mir
mattr-invalid-combination.ll
mem64.ll
mem.ll
mir-target-flags.ll
module-target-abi2.ll
module-target-abi.ll
mul.ll
musttail-call.ll
nomerge.ll
option-nopic.ll
option-norelax.ll
option-norvc.ll
option-pic.ll
option-relax.ll
option-rvc.ll
pic-models.ll
pr40333.ll
prefetch.ll
readcyclecounter.ll
rem.ll
remat.ll
reserved-reg-errors.ll
reserved-regs.ll
rotl-rotr.ll
rv32e.ll
rv32i-rv64i-float-double.ll
rv32Zbb.ll	[RISCV] Make ctlz/cttz cheap to speculatively execute so CodeGenPrepare won't insert a zero check.	2020-11-09 10:13:45 -08:00
rv32Zbbp.ll	[RISCV] Add isel patterns for using PACK for zext.h and zext.w.	2020-11-09 10:13:45 -08:00
rv32Zbp.ll	[RISCV] Add missing patterns for rotr with immediate for Zbb/Zbp extensions.	2020-11-03 10:04:52 -08:00
rv32Zbs.ll	[RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked.	2020-11-09 09:55:26 -08:00
rv32Zbt.ll	[RISCV] Add an ANDI to shift amount of FSL/FSR instructions	2020-11-12 07:33:40 -08:00
rv64-large-stack.ll
rv64d-double-convert.ll
rv64f-float-convert.ll
rv64i-complex-float.ll
rv64i-demanded-bits.ll	[RISCV] Improve worklist management in the DAG combine for SLLW/SRLW/SRAW	2020-10-29 14:52:53 -07:00
rv64i-double-softfloat.ll	[RISCV] Use the 'si' lib call for (double (fp_to_sint/uint i32 X)) when F extension is enabled.	2020-11-05 10:46:45 -08:00
rv64i-exhaustive-w-insts.ll
rv64i-single-softfloat.ll	Recommit "[RISCV] Move some test cases from rv64i-single-softfloat.ll to a new rv64i-double-softfloat.ll. NFC""	2020-11-04 19:58:11 -08:00
rv64i-tricky-shifts.ll
rv64i-w-insts-legalization.ll
rv64m-exhaustive-w-insts.ll
rv64m-w-insts-legalization.ll
rv64Zbb.ll	[RISCV] When matching SROIW, check all 64 bits of the OR mask	2020-11-16 10:08:15 -08:00
rv64Zbbp.ll	[RISCV] Add RORW/ROLW/RORIW/ROLIW test cases that don't sign extend the result. NFC	2020-11-13 10:59:32 -08:00
rv64Zbp.ll	[RISCV] Add test case showing failure to use GREVIW for i32 bitreverse if result is not sign extended. NFC	2020-11-13 12:41:41 -08:00
rv64Zbs.ll	[RISCV] Add isel patterns to match sbset/sbclr/sbinv/sbext even if the shift amount isn't masked.	2020-11-09 09:55:26 -08:00
rv64Zbt.ll	[RISCV] Add test cases for fsrw/fslw that don't sign extend the result. NFC	2020-11-13 23:31:16 -08:00
saverestore.ll
sdata-limit-0.ll
sdata-limit-4.ll
sdata-limit-8.ll
sdata-local-sym.ll
select-and.ll
select-cc.ll
select-const.ll
select-optimize-multiple.ll	[MachineSink] sink more profitable loads	2020-11-01 21:13:27 -05:00
select-optimize-multiple.mir
select-or.ll
setcc-logic.ll
sext-zext-trunc.ll
shadowcallstack.ll
shift-masked-shamt.ll
shifts.ll
shrinkwrap.ll
split-offsets.ll
split-sp-adjust.ll
srem-lkk.ll
srem-vector-lkk.ll	[RISCV] srem-vector-lkk.ll - remove unused check prefix	2020-11-11 18:38:23 +00:00
stack-realignment-with-variable-sized-objects.ll
stack-realignment.ll
stack-store-check.ll
subtarget-features-std-ext.ll
tail-calls.ll
target-abi-invalid.ll
target-abi-valid.ll
thread-pointer.ll
tls-models.ll
umulo-128-legalisation-lowering.ll
urem-lkk.ll
urem-vector-lkk.ll
vararg.ll
verify-instr.mir
wide-mem.ll
zext-with-load-is-free.ll