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95037fa9f6
Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
270 lines
7.5 KiB
LLVM
270 lines
7.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64IFD %s
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define float @fcvt_s_d(double %a) nounwind {
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; RV32IFD-LABEL: fcvt_s_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fcvt.s.d ft0, ft0
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; RV32IFD-NEXT: fmv.x.w a0, ft0
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_s_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fcvt.s.d ft0, ft0
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; RV64IFD-NEXT: fmv.x.w a0, ft0
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; RV64IFD-NEXT: ret
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%1 = fptrunc double %a to float
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ret float %1
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}
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define double @fcvt_d_s(float %a) nounwind {
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; RV32IFD-LABEL: fcvt_d_s:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: fmv.w.x ft0, a0
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; RV32IFD-NEXT: fcvt.d.s ft0, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_d_s:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.w.x ft0, a0
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; RV64IFD-NEXT: fcvt.d.s ft0, ft0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = fpext float %a to double
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ret double %1
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}
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; For RV64D, fcvt.l.d is semantically equivalent to fcvt.w.d in this case
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; because fptosi will produce poison if the result doesn't fit into an i32.
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define i32 @fcvt_w_d(double %a) nounwind {
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; RV32IFD-LABEL: fcvt_w_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fcvt.w.d a0, ft0, rtz
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_w_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
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; RV64IFD-NEXT: ret
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%1 = fptosi double %a to i32
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ret i32 %1
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}
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; For RV64D, fcvt.lu.d is semantically equivalent to fcvt.wu.d in this case
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; because fptosi will produce poison if the result doesn't fit into an i32.
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define i32 @fcvt_wu_d(double %a) nounwind {
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; RV32IFD-LABEL: fcvt_wu_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a0, 8(sp)
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; RV32IFD-NEXT: sw a1, 12(sp)
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; RV32IFD-NEXT: fld ft0, 8(sp)
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; RV32IFD-NEXT: fcvt.wu.d a0, ft0, rtz
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_wu_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
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; RV64IFD-NEXT: ret
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%1 = fptoui double %a to i32
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ret i32 %1
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}
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define double @fcvt_d_w(i32 %a) nounwind {
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; RV32IFD-LABEL: fcvt_d_w:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: fcvt.d.w ft0, a0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_d_w:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fcvt.d.w ft0, a0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = sitofp i32 %a to double
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ret double %1
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}
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define double @fcvt_d_wu(i32 %a) nounwind {
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; RV32IFD-LABEL: fcvt_d_wu:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: fcvt.d.wu ft0, a0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_d_wu:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fcvt.d.wu ft0, a0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = uitofp i32 %a to double
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ret double %1
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}
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define i64 @fcvt_l_d(double %a) nounwind {
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; RV32IFD-LABEL: fcvt_l_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: call __fixdfdi
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_l_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fcvt.l.d a0, ft0, rtz
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; RV64IFD-NEXT: ret
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%1 = fptosi double %a to i64
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ret i64 %1
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}
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define i64 @fcvt_lu_d(double %a) nounwind {
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; RV32IFD-LABEL: fcvt_lu_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: call __fixunsdfdi
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_lu_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fcvt.lu.d a0, ft0, rtz
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; RV64IFD-NEXT: ret
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%1 = fptoui double %a to i64
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ret i64 %1
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}
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define i64 @fmv_x_d(double %a, double %b) nounwind {
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; RV32IFD-LABEL: fmv_x_d:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw a2, 0(sp)
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; RV32IFD-NEXT: sw a3, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft1, 0(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fmv_x_d:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a1
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; RV64IFD-NEXT: fmv.d.x ft1, a0
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; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = fadd double %a, %b
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%2 = bitcast double %1 to i64
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ret i64 %2
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}
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define double @fcvt_d_l(i64 %a) nounwind {
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; RV32IFD-LABEL: fcvt_d_l:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: call __floatdidf
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_d_l:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fcvt.d.l ft0, a0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = sitofp i64 %a to double
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ret double %1
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}
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define double @fcvt_d_lu(i64 %a) nounwind {
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; RV32IFD-LABEL: fcvt_d_lu:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp)
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; RV32IFD-NEXT: call __floatundidf
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; RV32IFD-NEXT: lw ra, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 16
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fcvt_d_lu:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fcvt.d.lu ft0, a0
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = uitofp i64 %a to double
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ret double %1
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}
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define double @fmv_d_x(i64 %a, i64 %b) nounwind {
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; Ensure fmv.w.x is generated even for a soft double calling convention
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; RV32IFD-LABEL: fmv_d_x:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi sp, sp, -32
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; RV32IFD-NEXT: sw a3, 20(sp)
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; RV32IFD-NEXT: sw a2, 16(sp)
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; RV32IFD-NEXT: sw a1, 28(sp)
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; RV32IFD-NEXT: sw a0, 24(sp)
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; RV32IFD-NEXT: fld ft0, 16(sp)
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; RV32IFD-NEXT: fld ft1, 24(sp)
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; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
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; RV32IFD-NEXT: fsd ft0, 8(sp)
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; RV32IFD-NEXT: lw a0, 8(sp)
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; RV32IFD-NEXT: lw a1, 12(sp)
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; RV32IFD-NEXT: addi sp, sp, 32
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; RV32IFD-NEXT: ret
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;
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; RV64IFD-LABEL: fmv_d_x:
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; RV64IFD: # %bb.0:
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; RV64IFD-NEXT: fmv.d.x ft0, a0
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; RV64IFD-NEXT: fmv.d.x ft1, a1
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; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
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; RV64IFD-NEXT: fmv.x.d a0, ft0
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; RV64IFD-NEXT: ret
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%1 = bitcast i64 %a to double
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%2 = bitcast i64 %b to double
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%3 = fadd double %1, %2
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ret double %3
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}
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