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llvm-mirror/test/CodeGen/RISCV/flt-rounds.ll
Alex Bradbury b21bce1029 [SelectionDAG] Support result type promotion for FLT_ROUNDS_
For targets where i32 is not a legal type (e.g. 64-bit RISC-V), 
LegalizeIntegerTypes must promote the result of ISD::FLT_ROUNDS_.

Differential Revision: https://reviews.llvm.org/D53820

llvm-svn: 347986
2018-11-30 13:18:33 +00:00

22 lines
628 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
declare i32 @llvm.flt.rounds()
define i32 @test_flt_rounds() nounwind {
; RV32I-LABEL: test_flt_rounds:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_flt_rounds:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: ret
%1 = call i32 @llvm.flt.rounds()
ret i32 %1
}