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df38585f56
We already have special code (DAG combine support for FP_ROUND) to recognize cases where we an use a vector version of VLEDB to perform two floating-point truncates in parallel, but equivalent support for VLEDB (vector floating-point extends) has been missing so far. This patch adds corresponding DAG combine support for FP_EXTEND. llvm-svn: 349746
45 lines
1.3 KiB
LLVM
45 lines
1.3 KiB
LLVM
; Test conversions between different-sized float elements.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test cases where both elements of a v2f64 are converted to f32s.
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define void @f1(<2 x double> %val, <2 x float> *%ptr) {
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; CHECK-LABEL: f1:
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; CHECK: vledb {{%v[0-9]+}}, %v24, 0, 0
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; CHECK: br %r14
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%res = fptrunc <2 x double> %val to <2 x float>
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store <2 x float> %res, <2 x float> *%ptr
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ret void
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}
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; Test conversion of an f64 in a vector register to an f32.
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define float @f2(<2 x double> %vec) {
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; CHECK-LABEL: f2:
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; CHECK: wledb %f0, %v24, 0, 0
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; CHECK: br %r14
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%scalar = extractelement <2 x double> %vec, i32 0
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%ret = fptrunc double %scalar to float
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ret float %ret
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}
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; Test cases where even elements of a v4f32 are converted to f64s.
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define <2 x double> @f3(<4 x float> %vec) {
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; CHECK-LABEL: f3:
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; CHECK: vldeb %v24, {{%v[0-9]+}}
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; CHECK: br %r14
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%shuffle = shufflevector <4 x float> %vec, <4 x float> undef, <2 x i32> <i32 0, i32 2>
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%res = fpext <2 x float> %shuffle to <2 x double>
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ret <2 x double> %res
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}
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; Test conversion of an f32 in a vector register to an f64.
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define double @f4(<4 x float> %vec) {
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; CHECK-LABEL: f4:
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; CHECK: wldeb %f0, %v24
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; CHECK: br %r14
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%scalar = extractelement <4 x float> %vec, i32 0
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%ret = fpext float %scalar to double
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ret double %ret
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}
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