Alessandro Decina 770bc060c5 [BPF] add support for 32 bit registers in inline asm ... Add "w" constraint type which allows selecting 32 bit registers. 32 bit registers were added in https://reviews.llvm.org/rGca31c3bb3ff149850b664838fbbc7d40ce571879. Differential Revision: https://reviews.llvm.org/D102118		2021-05-16 11:01:47 -07:00
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Analysis	[NFC][X86][Costmodel] Add tests for load/store with i1 element type	2021-05-16 14:29:37 +03:00
Assembler	[IR] Introduce the opaque pointer type	2021-05-13 15:22:27 -07:00
Bindings
Bitcode	IR+AArch64: add a "swiftasync" argument attribute.	2021-05-14 11:43:58 +01:00
BugPoint
CodeGen	[BPF] add support for 32 bit registers in inline asm	2021-05-16 11:01:47 -07:00
DebugInfo	[Transforms][Debugify] Fix "Missing line" false alarm on PHI nodes	2021-05-14 14:06:13 +02:00
Demangle	[Demangle][Rust] Parse trait definitions	2021-05-15 23:52:25 +02:00
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation	Remove (unneeded) '-asan-use-after-return' from hoist-argument-init-insts.ll.	2021-05-14 11:55:23 -07:00
Integer
JitListener
Linker
LTO
MachineVerifier
MC	[llvm-mc][AArch64] HINT instruction disassembled as BTI	2021-05-14 10:05:37 +01:00
Object	[AMDGPU] Add gfx1034 target	2021-05-13 14:25:18 -04:00
ObjectYAML
Other	[Matrix] Fix some newpm check lines, which fail on some bots. (2)	2021-05-16 14:11:18 +01:00
SafepointIRVerifier
Support	[SystemZ][z/OS] Add the functions needed for handling EBCDIC I/O	2021-05-03 08:52:38 -04:00
SymbolRewriter
TableGen	[TableGen] Make the NUL character invalid in .td files	2021-05-13 10:17:45 -04:00
ThinLTO/X86
tools	[X86][Atom] Fix vector integer multiplication resource/throughputs	2021-05-15 14:25:48 +01:00
Transforms	[CPG][ARM] Optimize towards branch on zero in codegenprepare	2021-05-16 17:54:06 +01:00
Unit
Verifier	IR+AArch64: add a "swiftasync" argument attribute.	2021-05-14 11:43:58 +01:00
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh