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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 15:32:52 +01:00
llvm-mirror/test/CodeGen
Richard Sandiford 77f91408dd [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses
Unlike most -- hopefully "all other", but I'm still checking -- memory
instructions we support, LOAD REVERSED and STORE REVERSED may access
the memory location several times.  This means that they are not suitable
for volatile loads and stores.

This patch is a prerequisite for better atomic load and store support.
The same principle applies there: almost all memory instructions we
support are inherently atomic ("block concurrent"), but LOAD REVERSED
and STORE REVERSED are exceptions.

Other instructions continue to allow volatile operands.  I will add
positive "allows volatile" tests at the same time as the "allows atomic
load or store" tests.

llvm-svn: 183002
2013-05-31 13:25:22 +00:00
..
AArch64 Change how we iterate over relocations on ELF. 2013-05-30 03:05:14 +00:00
ARM Revert r182937 and r182877. 2013-05-30 20:37:52 +00:00
CPP
Generic Drop @llvm.annotation and @llvm.ptr.annotation intrinsics during codegen. 2013-05-21 14:37:16 +00:00
Hexagon Hexagon: Pass to replace tranfer/copy instructions into combine instruction 2013-05-14 18:54:06 +00:00
Inputs
MBlaze
Mips [mips] Big-endian code generation for atomic instructions. 2013-05-31 03:25:44 +00:00
MSP430 DAGCombiner: Simplify inverted bit tests 2013-05-08 06:44:42 +00:00
NVPTX [NVPTX] Re-enable support for virtual registers in the final output 2013-05-31 12:14:49 +00:00
PowerPC Change how we iterate over relocations on ELF. 2013-05-30 03:05:14 +00:00
R600 R600: Fix R600ControlFlowFinalizer not considering VTX_READ 128 bit dst reg 2013-05-23 18:26:42 +00:00
SI
SPARC [Sparc] Add support for leaf functions in sparc backend. 2013-05-29 04:46:31 +00:00
SystemZ [SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses 2013-05-31 13:25:22 +00:00
Thumb LocalStackSlotAllocation improvements 2013-04-30 20:04:37 +00:00
Thumb2 Fix ARM FastISel tests, as a first step to enabling ARM FastISel 2013-05-14 16:26:38 +00:00
X86 X86: change MOV64ri64i32 into MOV32ri64 2013-05-31 09:57:13 +00:00
XCore [XCore] Fix handling of functions where only the LR is spilled. 2013-05-09 16:43:42 +00:00