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665 lines
24 KiB
ArmAsm
665 lines
24 KiB
ArmAsm
@---
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@ Run these test in both Thumb1 and Thumb2 modes, as all of the encodings
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@ should be valid, and parse the same, in both.
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@---
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@ RUN: llvm-mc -triple=thumbv6-apple-darwin -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s
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@ RUN: llvm-mc -triple=thumbebv7-unknown-unknown -show-encoding < %s | FileCheck --check-prefix=CHECK-BE %s
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.syntax unified
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.globl _func
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ For complex constructs like shifter operands, check more thoroughly for them
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@ once then spot check that following instructions accept the form generally.
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@ This gives us good coverage while keeping the overall size of the test
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@ more reasonable.
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@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax.
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_func:
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@ CHECK: _func
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@------------------------------------------------------------------------------
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@ ADC (register)
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@------------------------------------------------------------------------------
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adcs r4, r6
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@ CHECK: adcs r4, r6 @ encoding: [0x74,0x41]
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@------------------------------------------------------------------------------
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@ ADD (immediate)
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@------------------------------------------------------------------------------
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adds r1, r2, #3
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@ When Rd is not explicitly specified, encoding T2 is preferred even though
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@ the literal is in the range [0,7] which would allow encoding T1.
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adds r2, #3
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adds r2, #8
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@ CHECK: adds r1, r2, #3 @ encoding: [0xd1,0x1c]
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@ CHECK: adds r2, #3 @ encoding: [0x03,0x32]
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@ CHECK: adds r2, #8 @ encoding: [0x08,0x32]
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@------------------------------------------------------------------------------
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@ ADD (register)
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@------------------------------------------------------------------------------
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adds r1, r2, r3
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add r2, r8
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@ CHECK: adds r1, r2, r3 @ encoding: [0xd1,0x18]
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@ CHECK: add r2, r8 @ encoding: [0x42,0x44]
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@------------------------------------------------------------------------------
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@ ADD (SP plus immediate)
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@------------------------------------------------------------------------------
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add sp, #4
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add sp, #508
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add sp, sp, #4
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add r2, sp, #8
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add r2, sp, #1020
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add sp, sp, #-8
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add sp, #-8
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@ CHECK: add sp, #4 @ encoding: [0x01,0xb0]
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@ CHECK: add sp, #508 @ encoding: [0x7f,0xb0]
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@ CHECK: add sp, #4 @ encoding: [0x01,0xb0]
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@ CHECK: add r2, sp, #8 @ encoding: [0x02,0xaa]
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@ CHECK: add r2, sp, #1020 @ encoding: [0xff,0xaa]
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@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
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@ CHECK: sub sp, #8 @ encoding: [0x82,0xb0]
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@------------------------------------------------------------------------------
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@ ADD (SP plus register)
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@------------------------------------------------------------------------------
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add sp, r3
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add r2, sp, r2
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@ CHECK: add sp, r3 @ encoding: [0x9d,0x44]
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@ CHECK: add r2, sp, r2 @ encoding: [0x6a,0x44]
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@------------------------------------------------------------------------------
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@ ADR
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@------------------------------------------------------------------------------
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adr r2, _baz
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adr r5, #0
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adr r2, #4
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adr r3, #1020
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@ CHECK: adr r2, _baz @ encoding: [A,0xa2]
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@ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
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@ CHECK-BE: adr r2, _baz @ encoding: [0xa2,A]
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@ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_thumb_adr_pcrel_10
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@ CHECK: adr r5, #0 @ encoding: [0x00,0xa5]
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@ CHECK: adr r2, #4 @ encoding: [0x01,0xa2]
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@ CHECK: adr r3, #1020 @ encoding: [0xff,0xa3]
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@------------------------------------------------------------------------------
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@ ASR (immediate)
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@------------------------------------------------------------------------------
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asrs r2, r3, #32
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asrs r2, r3, #5
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asrs r2, r3, #1
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asrs r5, #21
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asrs r5, r5, #21
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asrs r3, r5, #21
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@ CHECK: asrs r2, r3, #32 @ encoding: [0x1a,0x10]
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@ CHECK: asrs r2, r3, #5 @ encoding: [0x5a,0x11]
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@ CHECK: asrs r2, r3, #1 @ encoding: [0x5a,0x10]
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@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
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@ CHECK: asrs r5, r5, #21 @ encoding: [0x6d,0x15]
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@ CHECK: asrs r3, r5, #21 @ encoding: [0x6b,0x15]
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@------------------------------------------------------------------------------
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@ ASR (register)
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@------------------------------------------------------------------------------
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asrs r5, r2
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@ CHECK: asrs r5, r2 @ encoding: [0x15,0x41]
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@------------------------------------------------------------------------------
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@ B
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@------------------------------------------------------------------------------
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b _baz
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beq _bar
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b #1838
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b #-420
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beq #-256
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beq #160
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@ CHECK: b _baz @ encoding: [A,0xe0'A']
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@ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
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@ CHECK-BE: b _baz @ encoding: [0xe0'A',A]
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@ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_br
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@ CHECK: beq _bar @ encoding: [A,0xd0]
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@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
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@ CHECK-BE: beq _bar @ encoding: [0xd0,A]
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@ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bcc
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@ CHECK: b #1838 @ encoding: [0x97,0xe3]
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@ CHECK: b #-420 @ encoding: [0x2e,0xe7]
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@ CHECK: beq #-256 @ encoding: [0x80,0xd0]
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@ CHECK: beq #160 @ encoding: [0x50,0xd0]
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@------------------------------------------------------------------------------
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@ BL/BLX
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@------------------------------------------------------------------------------
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blx #884800
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blx #1769600
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@ CHECK: blx #884800 @ encoding: [0xd8,0xf0,0x20,0xe8]
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@ CHECK: blx #1769600 @ encoding: [0xb0,0xf1,0x40,0xe8]
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@------------------------------------------------------------------------------
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@ BICS
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@------------------------------------------------------------------------------
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bics r1, r6
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@ CHECK: bics r1, r6 @ encoding: [0xb1,0x43]
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@------------------------------------------------------------------------------
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@ BKPT
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@------------------------------------------------------------------------------
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bkpt #0
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bkpt #255
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@ CHECK: bkpt #0 @ encoding: [0x00,0xbe]
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@ CHECK: bkpt #255 @ encoding: [0xff,0xbe]
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@------------------------------------------------------------------------------
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@ BL/BLX (immediate)
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@------------------------------------------------------------------------------
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bl _bar
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blx _baz
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@ CHECK: bl _bar @ encoding: [A,0xf0'A',A,0xd0'A']
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@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
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@ CHECK-BE: bl _bar @ encoding: [0xf0'A',A,0xd0'A',A]
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@ CHECK-BE: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_thumb_bl
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@ CHECK: blx _baz @ encoding: [A,0xf0'A',A,0xc0'A']
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@ CHECK: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
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@ CHECK-BE: blx _baz @ encoding: [0xf0'A',A,0xc0'A',A]
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@ CHECK-BE: @ fixup A - offset: 0, value: _baz, kind: fixup_arm_thumb_blx
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@------------------------------------------------------------------------------
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@ BLX (register)
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@------------------------------------------------------------------------------
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blx r4
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@ CHECK: blx r4 @ encoding: [0xa0,0x47]
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@------------------------------------------------------------------------------
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@ BX
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@------------------------------------------------------------------------------
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bx r2
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@ CHECK: bx r2 @ encoding: [0x10,0x47]
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@------------------------------------------------------------------------------
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@ CMN
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@------------------------------------------------------------------------------
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cmn r5, r1
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@ CHECK: cmn r5, r1 @ encoding: [0xcd,0x42]
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@------------------------------------------------------------------------------
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@ CMP
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@------------------------------------------------------------------------------
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cmp r6, #32
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cmp r3, r4
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cmp r8, r1
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@ CHECK: cmp r6, #32 @ encoding: [0x20,0x2e]
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@ CHECK: cmp r3, r4 @ encoding: [0xa3,0x42]
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@ CHECK: cmp r8, r1 @ encoding: [0x88,0x45]
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@------------------------------------------------------------------------------
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@ CPS
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@------------------------------------------------------------------------------
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cpsie f
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cpsid a
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@ CHECK: cpsie f @ encoding: [0x61,0xb6]
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@ CHECK: cpsid a @ encoding: [0x74,0xb6]
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@------------------------------------------------------------------------------
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@ EOR
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@------------------------------------------------------------------------------
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eors r4, r5
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@ CHECK: eors r4, r5 @ encoding: [0x6c,0x40]
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@------------------------------------------------------------------------------
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@ LDM
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@------------------------------------------------------------------------------
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ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}
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ldm r2!, {r1, r3, r4, r5, r7}
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ldm r1, {r1}
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@ CHECK: ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7} @ encoding: [0xff,0xcb]
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@ CHECK: ldm r2!, {r1, r3, r4, r5, r7} @ encoding: [0xba,0xca]
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@ CHECK: ldm r1, {r1} @ encoding: [0x02,0xc9]
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@------------------------------------------------------------------------------
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@ LDR (immediate)
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@------------------------------------------------------------------------------
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ldr r1, [r5]
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ldr r2, [r6, #32]
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ldr r3, [r7, #124]
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ldr r1, [sp]
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ldr r2, [sp, #24]
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ldr r3, [sp, #1020]
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@ CHECK: ldr r1, [r5] @ encoding: [0x29,0x68]
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@ CHECK: ldr r2, [r6, #32] @ encoding: [0x32,0x6a]
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@ CHECK: ldr r3, [r7, #124] @ encoding: [0xfb,0x6f]
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@ CHECK: ldr r1, [sp] @ encoding: [0x00,0x99]
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@ CHECK: ldr r2, [sp, #24] @ encoding: [0x06,0x9a]
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@ CHECK: ldr r3, [sp, #1020] @ encoding: [0xff,0x9b]
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@------------------------------------------------------------------------------
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@ LDR (literal)
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@------------------------------------------------------------------------------
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ldr r1, _foo
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ldr r3, #604
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ldr r3, #368
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@ CHECK: ldr r1, _foo @ encoding: [A,0x49]
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@ CHECK: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
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@ CHECK-BE: ldr r1, _foo @ encoding: [0x49,A]
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@ CHECK-BE: @ fixup A - offset: 0, value: _foo, kind: fixup_arm_thumb_cp
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@ CHECK: ldr r3, [pc, #604] @ encoding: [0x97,0x4b]
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@ CHECK: ldr r3, [pc, #368] @ encoding: [0x5c,0x4b]
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@------------------------------------------------------------------------------
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@ LDR (register)
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@------------------------------------------------------------------------------
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ldr r1, [r2, r3]
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@ CHECK: ldr r1, [r2, r3] @ encoding: [0xd1,0x58]
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@------------------------------------------------------------------------------
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@ LDRB (immediate)
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@------------------------------------------------------------------------------
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ldrb r4, [r3]
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ldrb r5, [r6, #0]
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ldrb r6, [r7, #31]
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@ CHECK: ldrb r4, [r3] @ encoding: [0x1c,0x78]
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@ CHECK: ldrb r5, [r6] @ encoding: [0x35,0x78]
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@ CHECK: ldrb r6, [r7, #31] @ encoding: [0xfe,0x7f]
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@------------------------------------------------------------------------------
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@ LDRB (register)
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@------------------------------------------------------------------------------
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ldrb r6, [r4, r5]
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@ CHECK: ldrb r6, [r4, r5] @ encoding: [0x66,0x5d]
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@------------------------------------------------------------------------------
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@ LDRH (immediate)
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@------------------------------------------------------------------------------
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ldrh r3, [r3]
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ldrh r4, [r6, #2]
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ldrh r5, [r7, #62]
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@ CHECK: ldrh r3, [r3] @ encoding: [0x1b,0x88]
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@ CHECK: ldrh r4, [r6, #2] @ encoding: [0x74,0x88]
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@ CHECK: ldrh r5, [r7, #62] @ encoding: [0xfd,0x8f]
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@------------------------------------------------------------------------------
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@ LDRH (register)
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@------------------------------------------------------------------------------
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ldrh r6, [r2, r6]
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@ CHECK: ldrh r6, [r2, r6] @ encoding: [0x96,0x5b]
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@------------------------------------------------------------------------------
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@ LDRSB/LDRSH
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@------------------------------------------------------------------------------
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ldrsb r6, [r2, r6]
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ldrsh r3, [r7, r1]
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@ CHECK: ldrsb r6, [r2, r6] @ encoding: [0x96,0x57]
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@ CHECK: ldrsh r3, [r7, r1] @ encoding: [0x7b,0x5e]
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@------------------------------------------------------------------------------
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@ LSL (immediate)
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@------------------------------------------------------------------------------
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lsls r4, r5, #0
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lsls r4, r5, #4
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lsls r3, #12
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lsls r3, r3, #12
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lsls r1, r3, #12
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@ CHECK: lsls r4, r5, #0 @ encoding: [0x2c,0x00]
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@ CHECK: lsls r4, r5, #4 @ encoding: [0x2c,0x01]
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@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
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@ CHECK: lsls r3, r3, #12 @ encoding: [0x1b,0x03]
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@ CHECK: lsls r1, r3, #12 @ encoding: [0x19,0x03]
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@------------------------------------------------------------------------------
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@ LSL (register)
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@------------------------------------------------------------------------------
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lsls r2, r6
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@ CHECK: lsls r2, r6 @ encoding: [0xb2,0x40]
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@------------------------------------------------------------------------------
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@ LSR (immediate)
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@------------------------------------------------------------------------------
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lsrs r1, r3, #1
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lsrs r1, r3, #32
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lsrs r4, #20
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lsrs r4, r4, #20
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lsrs r2, r4, #20
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@ CHECK: lsrs r1, r3, #1 @ encoding: [0x59,0x08]
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@ CHECK: lsrs r1, r3, #32 @ encoding: [0x19,0x08]
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@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
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@ CHECK: lsrs r4, r4, #20 @ encoding: [0x24,0x0d]
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@ CHECK: lsrs r2, r4, #20 @ encoding: [0x22,0x0d]
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@------------------------------------------------------------------------------
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@ LSR (register)
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@------------------------------------------------------------------------------
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lsrs r2, r6
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@ CHECK: lsrs r2, r6 @ encoding: [0xf2,0x40]
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@------------------------------------------------------------------------------
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@ MOV (immediate)
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@------------------------------------------------------------------------------
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movs r2, #0
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movs r2, #255
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movs r2, #23
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@ CHECK: movs r2, #0 @ encoding: [0x00,0x22]
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@ CHECK: movs r2, #255 @ encoding: [0xff,0x22]
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@ CHECK: movs r2, #23 @ encoding: [0x17,0x22]
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@------------------------------------------------------------------------------
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@ MOV (register)
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@------------------------------------------------------------------------------
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mov r3, r4
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movs r1, r3
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@ CHECK: mov r3, r4 @ encoding: [0x23,0x46]
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@ CHECK: movs r1, r3 @ encoding: [0x19,0x00]
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@------------------------------------------------------------------------------
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@ MUL
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@------------------------------------------------------------------------------
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muls r1, r2, r1
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muls r2, r2, r3
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muls r3, r4
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@ CHECK: muls r1, r2, r1 @ encoding: [0x51,0x43]
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@ CHECK: muls r2, r3, r2 @ encoding: [0x5a,0x43]
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@ CHECK: muls r3, r4, r3 @ encoding: [0x63,0x43]
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@------------------------------------------------------------------------------
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@ MVN
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@------------------------------------------------------------------------------
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mvns r6, r3
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@ CHECK: mvns r6, r3 @ encoding: [0xde,0x43]
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@------------------------------------------------------------------------------
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@ NEG
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@------------------------------------------------------------------------------
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negs r3, r4
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@ CHECK: rsbs r3, r4, #0 @ encoding: [0x63,0x42]
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@------------------------------------------------------------------------------
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@ ORR
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@------------------------------------------------------------------------------
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orrs r3, r4
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@ CHECK-ERRORS: orrs r3, r4 @ encoding: [0x23,0x43]
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@------------------------------------------------------------------------------
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@ POP
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@------------------------------------------------------------------------------
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pop {r2, r3, r6}
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@ CHECK: pop {r2, r3, r6} @ encoding: [0x4c,0xbc]
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@------------------------------------------------------------------------------
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@ PUSH
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@------------------------------------------------------------------------------
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push {r1, r2, r7}
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@ CHECK: push {r1, r2, r7} @ encoding: [0x86,0xb4]
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@------------------------------------------------------------------------------
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@ REV/REV16/REVSH
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@------------------------------------------------------------------------------
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rev r6, r3
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rev16 r7, r2
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revsh r5, r1
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@ CHECK: rev r6, r3 @ encoding: [0x1e,0xba]
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@ CHECK: rev16 r7, r2 @ encoding: [0x57,0xba]
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@ CHECK: revsh r5, r1 @ encoding: [0xcd,0xba]
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@------------------------------------------------------------------------------
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@ ROR
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@------------------------------------------------------------------------------
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rors r2, r7
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@ CHECK: rors r2, r7 @ encoding: [0xfa,0x41]
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|
|
@------------------------------------------------------------------------------
|
|
@ RSB
|
|
@------------------------------------------------------------------------------
|
|
rsbs r1, r3, #0
|
|
|
|
@ CHECK: rsbs r1, r3, #0 @ encoding: [0x59,0x42]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SBC
|
|
@------------------------------------------------------------------------------
|
|
sbcs r4, r3
|
|
|
|
@ CHECK: sbcs r4, r3 @ encoding: [0x9c,0x41]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SETEND
|
|
@------------------------------------------------------------------------------
|
|
setend be
|
|
setend le
|
|
|
|
@ CHECK: setend be @ encoding: [0x58,0xb6]
|
|
@ CHECK: setend le @ encoding: [0x50,0xb6]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STM
|
|
@------------------------------------------------------------------------------
|
|
stm r1!, {r2, r6}
|
|
stm r1!, {r1, r2, r3, r7}
|
|
|
|
@ CHECK: stm r1!, {r2, r6} @ encoding: [0x44,0xc1]
|
|
@ CHECK: stm r1!, {r1, r2, r3, r7} @ encoding: [0x8e,0xc1]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STR (immediate)
|
|
@------------------------------------------------------------------------------
|
|
str r2, [r7]
|
|
str r2, [r7, #0]
|
|
str r5, [r1, #4]
|
|
str r3, [r7, #124]
|
|
str r2, [sp]
|
|
str r3, [sp, #0]
|
|
str r4, [sp, #20]
|
|
str r5, [sp, #1020]
|
|
|
|
@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60]
|
|
@ CHECK: str r2, [r7] @ encoding: [0x3a,0x60]
|
|
@ CHECK: str r5, [r1, #4] @ encoding: [0x4d,0x60]
|
|
@ CHECK: str r3, [r7, #124] @ encoding: [0xfb,0x67]
|
|
@ CHECK: str r2, [sp] @ encoding: [0x00,0x92]
|
|
@ CHECK: str r3, [sp] @ encoding: [0x00,0x93]
|
|
@ CHECK: str r4, [sp, #20] @ encoding: [0x05,0x94]
|
|
@ CHECK: str r5, [sp, #1020] @ encoding: [0xff,0x95]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STR (register)
|
|
@------------------------------------------------------------------------------
|
|
str r2, [r7, r3]
|
|
|
|
@ CHECK: str r2, [r7, r3] @ encoding: [0xfa,0x50]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STRB (immediate)
|
|
@------------------------------------------------------------------------------
|
|
strb r4, [r3]
|
|
strb r5, [r6, #0]
|
|
strb r6, [r7, #31]
|
|
|
|
@ CHECK: strb r4, [r3] @ encoding: [0x1c,0x70]
|
|
@ CHECK: strb r5, [r6] @ encoding: [0x35,0x70]
|
|
@ CHECK: strb r6, [r7, #31] @ encoding: [0xfe,0x77]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STRB (register)
|
|
@------------------------------------------------------------------------------
|
|
strb r6, [r4, r5]
|
|
|
|
@ CHECK: strb r6, [r4, r5] @ encoding: [0x66,0x55]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STRH (immediate)
|
|
@------------------------------------------------------------------------------
|
|
strh r3, [r3]
|
|
strh r4, [r6, #2]
|
|
strh r5, [r7, #62]
|
|
|
|
@ CHECK: strh r3, [r3] @ encoding: [0x1b,0x80]
|
|
@ CHECK: strh r4, [r6, #2] @ encoding: [0x74,0x80]
|
|
@ CHECK: strh r5, [r7, #62] @ encoding: [0xfd,0x87]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ STRH (register)
|
|
@------------------------------------------------------------------------------
|
|
strh r6, [r2, r6]
|
|
|
|
@ CHECK: strh r6, [r2, r6] @ encoding: [0x96,0x53]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SUB (immediate)
|
|
@------------------------------------------------------------------------------
|
|
subs r1, r2, #3
|
|
subs r2, #3
|
|
subs r2, #8
|
|
|
|
@ CHECK: subs r1, r2, #3 @ encoding: [0xd1,0x1e]
|
|
@ CHECK: subs r2, #3 @ encoding: [0x03,0x3a]
|
|
@ CHECK: subs r2, #8 @ encoding: [0x08,0x3a]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SUB (SP minus immediate)
|
|
@------------------------------------------------------------------------------
|
|
sub sp, #12
|
|
sub sp, sp, #508
|
|
|
|
@ CHECK: sub sp, #12 @ encoding: [0x83,0xb0]
|
|
@ CHECK: sub sp, #508 @ encoding: [0xff,0xb0]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SUB (register)
|
|
@------------------------------------------------------------------------------
|
|
subs r1, r2, r3
|
|
|
|
@ CHECK: subs r1, r2, r3 @ encoding: [0xd1,0x1a]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SVC
|
|
@------------------------------------------------------------------------------
|
|
svc #0
|
|
svc #255
|
|
|
|
@ CHECK: svc #0 @ encoding: [0x00,0xdf]
|
|
@ CHECK: svc #255 @ encoding: [0xff,0xdf]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ SXTB/SXTH
|
|
@------------------------------------------------------------------------------
|
|
sxtb r3, r5
|
|
sxth r3, r5
|
|
|
|
@ CHECK: sxtb r3, r5 @ encoding: [0x6b,0xb2]
|
|
@ CHECK: sxth r3, r5 @ encoding: [0x2b,0xb2]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ TST
|
|
@------------------------------------------------------------------------------
|
|
tst r6, r1
|
|
|
|
@ CHECK: tst r6, r1 @ encoding: [0x0e,0x42]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ UXTB/UXTH
|
|
@------------------------------------------------------------------------------
|
|
uxtb r7, r2
|
|
uxth r1, r4
|
|
|
|
@ CHECK: uxtb r7, r2 @ encoding: [0xd7,0xb2]
|
|
@ CHECK: uxth r1, r4 @ encoding: [0xa1,0xb2]
|
|
|
|
|