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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-02 00:42:52 +01:00
llvm-mirror/test/CodeGen
Bruno Cardoso Lopes 7cb26cb8be - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary.
- Make foldMemoryOperandImpl aware of 256-bit zero vectors folding and support the 128-bit counterparts of AVX too.
- Make sure MOV[AU]PS instructions are only selected when SSE1 is enabled, and duplicate the patterns to match AVX.
- Add a testcase for a simple 128-bit zero vector creation.

llvm-svn: 110946
2010-08-12 20:20:53 +00:00
..
Alpha PR7774: Fix undefined shifts in Alpha backend. As a bonus, this actually 2010-08-01 21:13:28 +00:00
ARM Consider this code snippet: 2010-08-11 08:43:16 +00:00
Blackfin Remove TargetInstrInfo::copyRegToReg entirely. 2010-07-11 17:01:17 +00:00
CBackend
CellSPU Have SPU handle halfvec stores aligned by 8 bytes. 2010-08-09 16:33:00 +00:00
CPP
Generic Fix a crash in the dag combiner caused by ConstantFoldBIT_CONVERTofBUILD_VECTOR calling itself 2010-07-27 18:02:18 +00:00
MBlaze
Mips Fix PR7174, a couple o Mips fixes: 2010-07-20 08:37:04 +00:00
MSP430 Insert ANY_EXTEND node instead of invalid truncate during DAG Combining (X & 1), 2010-05-01 12:52:34 +00:00
PIC16
PowerPC PR7781: Fix incorrect shifting in PPCTargetLowering::LowerBUILD_VECTOR. 2010-08-02 00:18:19 +00:00
SPARC
SystemZ SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and 2010-05-14 22:17:42 +00:00
Thumb Fix test and re-enable it. 2010-08-11 17:25:51 +00:00
Thumb2 fix silly typo 2010-08-11 17:32:46 +00:00
X86 - Teach SSEDomainFix to switch between different levels of AVX instructions. Here we guess that AVX will have domain issues, so just implement them for consistency and in the future we remove if it's unnecessary. 2010-08-12 20:20:53 +00:00
XCore Start function numbering at 0. 2010-04-17 16:29:15 +00:00