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2bc932f596
The motivation for this is that I'm looking at an example that uses shifts as induction variables. There's lots of other omissions, but one of the first I noticed is that we can't compute tight known bits. (This indirectly causes SCEV's range analysis to produce very poor results as well.) Differential Revision: https://reviews.llvm.org/D96440
155 lines
4.1 KiB
LLVM
155 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -instcombine -S | FileCheck %s
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define i64 @test_lshr() {
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; CHECK-LABEL: @test_lshr(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 1023
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;
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entry:
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br label %loop
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loop:
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%iv.lshr = phi i64 [1023, %entry], [%iv.lshr.next, %loop]
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%iv.lshr.next = lshr i64 %iv.lshr, 1
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br i1 undef, label %exit, label %loop
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exit:
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%res = or i64 %iv.lshr, 1023
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ret i64 %res
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}
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define i64 @test_ashr_zeros() {
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; CHECK-LABEL: @test_ashr_zeros(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 1023
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;
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entry:
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br label %loop
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loop:
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%iv.ashr = phi i64 [1023, %entry], [%iv.ashr.next, %loop]
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%iv.ashr.next = ashr i64 %iv.ashr, 1
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br i1 undef, label %exit, label %loop
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exit:
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%res = or i64 %iv.ashr, 1023
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ret i64 %res
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}
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define i64 @test_ashr_ones() {
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; CHECK-LABEL: @test_ashr_ones(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 -1
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;
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entry:
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br label %loop
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loop:
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%iv.ashr = phi i64 [-1023, %entry], [%iv.ashr.next, %loop]
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%iv.ashr.next = ashr i64 %iv.ashr, 1
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br i1 undef, label %exit, label %loop
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exit:
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%res = or i64 %iv.ashr, 1023
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ret i64 %res
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}
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; Same as previous, but swapped operands to phi
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define i64 @test_ashr_ones2() {
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; CHECK-LABEL: @test_ashr_ones2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 -1
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;
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entry:
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br label %loop
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loop:
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%iv.ashr = phi i64 [%iv.ashr.next, %loop], [-1023, %entry]
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%iv.ashr.next = ashr i64 %iv.ashr, 1
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br i1 undef, label %exit, label %loop
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exit:
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%res = or i64 %iv.ashr, 1023
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ret i64 %res
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}
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; negative case for when start is unknown
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define i64 @test_ashr_unknown(i64 %start) {
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; CHECK-LABEL: @test_ashr_unknown(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV_ASHR:%.*]] = phi i64 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_ASHR_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_ASHR_NEXT]] = ashr i64 [[IV_ASHR]], 1
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = or i64 [[IV_ASHR]], 1023
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop]
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%iv.ashr.next = ashr i64 %iv.ashr, 1
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br i1 undef, label %exit, label %loop
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exit:
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%res = or i64 %iv.ashr, 1023
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ret i64 %res
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}
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; Negative case where we don't have a (shift) recurrence because the operands
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; of the ashr are swapped. (This does end up being a divide recurrence.)
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define i64 @test_ashr_wrong_op(i64 %start) {
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; CHECK-LABEL: @test_ashr_wrong_op(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV_ASHR:%.*]] = phi i64 [ [[START:%.*]], [[ENTRY:%.*]] ], [ [[IV_ASHR_NEXT:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[IV_ASHR_NEXT]] = lshr i64 1, [[IV_ASHR]]
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: [[RES:%.*]] = or i64 [[IV_ASHR]], 1023
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; CHECK-NEXT: ret i64 [[RES]]
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;
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entry:
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br label %loop
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loop:
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%iv.ashr = phi i64 [%start, %entry], [%iv.ashr.next, %loop]
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%iv.ashr.next = ashr i64 1, %iv.ashr
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br i1 undef, label %exit, label %loop
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exit:
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%res = or i64 %iv.ashr, 1023
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ret i64 %res
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}
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define i64 @test_shl() {
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; CHECK-LABEL: @test_shl(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: br i1 undef, label [[EXIT:%.*]], label [[LOOP]]
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; CHECK: exit:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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br label %loop
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loop:
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%iv.shl = phi i64 [8, %entry], [%iv.shl.next, %loop]
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%iv.shl.next = shl i64 %iv.shl, 1
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br i1 undef, label %exit, label %loop
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exit:
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%res = and i64 %iv.shl, 7
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ret i64 %res
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}
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