mirror of
https://github.com/RPCS3/llvm-mirror.git
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4c1f3c24db
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. llvm-svn: 171366
456 lines
14 KiB
C++
456 lines
14 KiB
C++
//===-- MipsLongBranch.cpp - Emit long branches ---------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass expands a branch or jump instruction into a long branch if its
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// offset is too large to fit into its immediate field.
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//
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// FIXME:
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// 1. Fix pc-region jump instructions which cross 256MB segment boundaries.
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// 2. If program has inline assembly statements whose size cannot be
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// determined accurately, load branch target addresses from the GOT.
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-long-branch"
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#include "Mips.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/IR/Function.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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STATISTIC(LongBranches, "Number of long branches.");
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static cl::opt<bool> SkipLongBranch(
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"skip-mips-long-branch",
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cl::init(false),
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cl::desc("MIPS: Skip long branch pass."),
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cl::Hidden);
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static cl::opt<bool> ForceLongBranch(
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"force-mips-long-branch",
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cl::init(false),
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cl::desc("MIPS: Expand all branches to long format."),
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cl::Hidden);
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namespace {
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typedef MachineBasicBlock::iterator Iter;
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typedef MachineBasicBlock::reverse_iterator ReverseIter;
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struct MBBInfo {
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uint64_t Size, Address;
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bool HasLongBranch;
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MachineInstr *Br;
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MBBInfo() : Size(0), HasLongBranch(false), Br(0) {}
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};
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class MipsLongBranch : public MachineFunctionPass {
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public:
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static char ID;
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MipsLongBranch(TargetMachine &tm)
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: MachineFunctionPass(ID), TM(tm),
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TII(static_cast<const MipsInstrInfo*>(tm.getInstrInfo())),
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IsPIC(TM.getRelocationModel() == Reloc::PIC_),
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ABI(TM.getSubtarget<MipsSubtarget>().getTargetABI()),
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LongBranchSeqSize(!IsPIC ? 2 : (ABI == MipsSubtarget::N64 ? 13 : 9)) {}
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virtual const char *getPassName() const {
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return "Mips Long Branch";
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}
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bool runOnMachineFunction(MachineFunction &F);
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private:
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void splitMBB(MachineBasicBlock *MBB);
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void initMBBInfo();
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int64_t computeOffset(const MachineInstr *Br);
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void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
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MachineBasicBlock *MBBOpnd);
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void expandToLongBranch(MBBInfo &Info);
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const TargetMachine &TM;
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const MipsInstrInfo *TII;
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MachineFunction *MF;
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SmallVector<MBBInfo, 16> MBBInfos;
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bool IsPIC;
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unsigned ABI;
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unsigned LongBranchSeqSize;
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};
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char MipsLongBranch::ID = 0;
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} // end of anonymous namespace
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/// createMipsLongBranchPass - Returns a pass that converts branches to long
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/// branches.
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FunctionPass *llvm::createMipsLongBranchPass(MipsTargetMachine &tm) {
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return new MipsLongBranch(tm);
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}
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/// Iterate over list of Br's operands and search for a MachineBasicBlock
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/// operand.
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static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
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for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
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const MachineOperand &MO = Br.getOperand(I);
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if (MO.isMBB())
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return MO.getMBB();
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}
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assert(false && "This instruction does not have an MBB operand.");
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return 0;
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}
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// Traverse the list of instructions backwards until a non-debug instruction is
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// found or it reaches E.
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static ReverseIter getNonDebugInstr(ReverseIter B, ReverseIter E) {
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for (; B != E; ++B)
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if (!B->isDebugValue())
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return B;
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return E;
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}
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// Split MBB if it has two direct jumps/branches.
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void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
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ReverseIter End = MBB->rend();
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ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
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// Return if MBB has no branch instructions.
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if ((LastBr == End) ||
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(!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
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return;
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ReverseIter FirstBr = getNonDebugInstr(llvm::next(LastBr), End);
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// MBB has only one branch instruction if FirstBr is not a branch
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// instruction.
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if ((FirstBr == End) ||
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(!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
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return;
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assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
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// Create a new MBB. Move instructions in MBB to the newly created MBB.
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MachineBasicBlock *NewMBB =
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MF->CreateMachineBasicBlock(MBB->getBasicBlock());
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// Insert NewMBB and fix control flow.
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MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
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NewMBB->transferSuccessors(MBB);
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NewMBB->removeSuccessor(Tgt);
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MBB->addSuccessor(NewMBB);
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MBB->addSuccessor(Tgt);
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MF->insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
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NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end());
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}
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// Fill MBBInfos.
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void MipsLongBranch::initMBBInfo() {
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// Split the MBBs if they have two branches. Each basic block should have at
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// most one branch after this loop is executed.
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for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E;)
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splitMBB(I++);
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MF->RenumberBlocks();
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MBBInfos.clear();
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MBBInfos.resize(MF->size());
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for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
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MachineBasicBlock *MBB = MF->getBlockNumbered(I);
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// Compute size of MBB.
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for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
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MI != MBB->instr_end(); ++MI)
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MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
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// Search for MBB's branch instruction.
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ReverseIter End = MBB->rend();
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ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
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if ((Br != End) && !Br->isIndirectBranch() &&
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(Br->isConditionalBranch() ||
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(Br->isUnconditionalBranch() &&
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TM.getRelocationModel() == Reloc::PIC_)))
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MBBInfos[I].Br = (++Br).base();
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}
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}
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// Compute offset of branch in number of bytes.
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int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
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int64_t Offset = 0;
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int ThisMBB = Br->getParent()->getNumber();
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int TargetMBB = getTargetMBB(*Br)->getNumber();
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// Compute offset of a forward branch.
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if (ThisMBB < TargetMBB) {
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for (int N = ThisMBB + 1; N < TargetMBB; ++N)
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Offset += MBBInfos[N].Size;
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return Offset + 4;
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}
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// Compute offset of a backward branch.
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for (int N = ThisMBB; N >= TargetMBB; --N)
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Offset += MBBInfos[N].Size;
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return -Offset + 4;
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}
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// Replace Br with a branch which has the opposite condition code and a
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// MachineBasicBlock operand MBBOpnd.
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void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
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DebugLoc DL, MachineBasicBlock *MBBOpnd) {
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unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode());
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const MCInstrDesc &NewDesc = TII->get(NewOpc);
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MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
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for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
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MachineOperand &MO = Br->getOperand(I);
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if (!MO.isReg()) {
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assert(MO.isMBB() && "MBB operand expected.");
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break;
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}
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MIB.addReg(MO.getReg());
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}
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MIB.addMBB(MBBOpnd);
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Br->eraseFromParent();
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}
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// Expand branch instructions to long branches.
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void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
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MachineBasicBlock::iterator Pos;
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MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
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DebugLoc DL = I.Br->getDebugLoc();
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const BasicBlock *BB = MBB->getBasicBlock();
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MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
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MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
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MF->insert(FallThroughMBB, LongBrMBB);
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MBB->removeSuccessor(TgtMBB);
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MBB->addSuccessor(LongBrMBB);
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if (IsPIC) {
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MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
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MF->insert(FallThroughMBB, BalTgtMBB);
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LongBrMBB->addSuccessor(BalTgtMBB);
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BalTgtMBB->addSuccessor(TgtMBB);
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int64_t TgtAddress = MBBInfos[TgtMBB->getNumber()].Address;
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unsigned BalTgtMBBSize = 5;
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int64_t Offset = TgtAddress - (I.Address + I.Size - BalTgtMBBSize * 4);
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int64_t Lo = SignExtend64<16>(Offset & 0xffff);
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int64_t Hi = SignExtend64<16>(((Offset + 0x8000) >> 16) & 0xffff);
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if (ABI != MipsSubtarget::N64) {
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// $longbr:
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// addiu $sp, $sp, -8
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// sw $ra, 0($sp)
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// bal $baltgt
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// lui $at, %hi($tgt - $baltgt)
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// $baltgt:
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// addiu $at, $at, %lo($tgt - $baltgt)
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// addu $at, $ra, $at
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// lw $ra, 0($sp)
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// jr $at
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// addiu $sp, $sp, 8
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// $fallthrough:
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//
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Pos = LongBrMBB->begin();
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(-8);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
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.addReg(Mips::SP).addImm(0);
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
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Pos = BalTgtMBB->begin();
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::AT)
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.addReg(Mips::AT).addImm(Lo);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
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.addReg(Mips::RA).addReg(Mips::AT);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
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.addReg(Mips::SP).addImm(0);
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MIBundleBuilder(*BalTgtMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
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.append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
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.addReg(Mips::SP).addImm(8));
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} else {
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// $longbr:
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// daddiu $sp, $sp, -16
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// sd $ra, 0($sp)
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// lui64 $at, %highest($tgt - $baltgt)
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// daddiu $at, $at, %higher($tgt - $baltgt)
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// dsll $at, $at, 16
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// daddiu $at, $at, %hi($tgt - $baltgt)
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// bal $baltgt
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// dsll $at, $at, 16
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// $baltgt:
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// daddiu $at, $at, %lo($tgt - $baltgt)
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// daddu $at, $ra, $at
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// ld $ra, 0($sp)
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// jr64 $at
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// daddiu $sp, $sp, 16
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// $fallthrough:
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//
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int64_t Higher = SignExtend64<16>(((Offset + 0x80008000) >> 32) & 0xffff);
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int64_t Highest =
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SignExtend64<16>(((Offset + 0x800080008000LL) >> 48) & 0xffff);
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Pos = LongBrMBB->begin();
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
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.addReg(Mips::SP_64).addImm(-16);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
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.addReg(Mips::SP_64).addImm(0);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LUi64), Mips::AT_64)
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.addImm(Highest);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Higher);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(16);
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BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Hi);
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::BAL_BR)).addMBB(BalTgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::DSLL), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(16));
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Pos = BalTgtMBB->begin();
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::AT_64)
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.addReg(Mips::AT_64).addImm(Lo);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
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.addReg(Mips::RA_64).addReg(Mips::AT_64);
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BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
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.addReg(Mips::SP_64).addImm(0);
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MIBundleBuilder(*BalTgtMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
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.append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
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.addReg(Mips::SP_64).addImm(16));
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}
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assert(BalTgtMBBSize == BalTgtMBB->size());
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assert(LongBrMBB->size() + BalTgtMBBSize == LongBranchSeqSize);
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} else {
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// $longbr:
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// j $tgt
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// nop
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// $fallthrough:
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//
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Pos = LongBrMBB->begin();
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LongBrMBB->addSuccessor(TgtMBB);
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MIBundleBuilder(*LongBrMBB, Pos)
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.append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
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.append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
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assert(LongBrMBB->size() == LongBranchSeqSize);
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}
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if (I.Br->isUnconditionalBranch()) {
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// Change branch destination.
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assert(I.Br->getDesc().getNumOperands() == 1);
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I.Br->RemoveOperand(0);
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I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
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} else
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// Change branch destination and reverse condition.
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replaceBranch(*MBB, I.Br, DL, FallThroughMBB);
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}
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static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
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MachineBasicBlock &MBB = F.front();
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MachineBasicBlock::iterator I = MBB.begin();
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DebugLoc DL = MBB.findDebugLoc(MBB.begin());
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BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
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.addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
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.addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
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MBB.removeLiveIn(Mips::V0);
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}
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bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
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if ((TM.getRelocationModel() == Reloc::PIC_) &&
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TM.getSubtarget<MipsSubtarget>().isABI_O32() &&
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F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
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emitGPDisp(F, TII);
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if (SkipLongBranch)
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return true;
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MF = &F;
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initMBBInfo();
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SmallVector<MBBInfo, 16>::iterator I, E = MBBInfos.end();
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bool EverMadeChange = false, MadeChange = true;
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while (MadeChange) {
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MadeChange = false;
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for (I = MBBInfos.begin(); I != E; ++I) {
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// Skip if this MBB doesn't have a branch or the branch has already been
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// converted to a long branch.
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if (!I->Br || I->HasLongBranch)
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continue;
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// Check if offset fits into 16-bit immediate field of branches.
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if (!ForceLongBranch && isInt<16>(computeOffset(I->Br) / 4))
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continue;
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I->HasLongBranch = true;
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I->Size += LongBranchSeqSize * 4;
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++LongBranches;
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EverMadeChange = MadeChange = true;
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}
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}
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if (!EverMadeChange)
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return true;
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// Compute basic block addresses.
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if (TM.getRelocationModel() == Reloc::PIC_) {
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uint64_t Address = 0;
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for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I)
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I->Address = Address;
|
|
}
|
|
|
|
// Do the expansion.
|
|
for (I = MBBInfos.begin(); I != E; ++I)
|
|
if (I->HasLongBranch)
|
|
expandToLongBranch(*I);
|
|
|
|
MF->RenumberBlocks();
|
|
|
|
return true;
|
|
}
|