Simon Pilgrim 7889ea478c [AARCH64][NEON] Add support for ISD::ABS lowering ... Update int_aarch64_neon_abs intrinsic to use the ISD::ABS opcode directly Differential Revision: https://reviews.llvm.org/D32940 llvm-svn: 302415		2017-05-08 10:25:18 +00:00
..
AsmParser	[Arch64AsmParser] better diagnostic for isb	2017-04-24 08:22:20 +00:00
Disassembler
InstPrinter	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
MCTargetDesc	[AArch64] ILP32 Backend Relocation Support	2017-05-02 22:01:48 +00:00
TargetInfo
Utils	[AArch64AsmParser] rewrite of function parseSysAlias	2017-03-03 08:12:47 +00:00
AArch64.h	[AArch64] Remove AArch64AddressTypePromotion pass	2017-05-05 16:05:41 +00:00
AArch64.td	[AArch64] armv8-A doesn't have CRC.	2017-05-03 20:33:52 +00:00
AArch64A53Fix835769.cpp
AArch64A57FPLoadBalancing.cpp
AArch64AdvSIMDScalarPass.cpp
AArch64AsmPrinter.cpp	[AArch64] ILP32 Backend Relocation Support	2017-05-02 22:01:48 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td
AArch64CallLowering.cpp	[IR] Abstract away ArgNo+1 attribute indexing as much as possible	2017-05-03 18:17:31 +00:00
AArch64CallLowering.h	[GlobalISel] Use the correct calling conv for calls	2017-03-20 14:40:18 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp
AArch64CollectLOH.cpp
AArch64ConditionalCompares.cpp
AArch64ConditionOptimizer.cpp
AArch64DeadRegisterDefinitionsPass.cpp
AArch64ExpandPseudoInsts.cpp	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
AArch64FastISel.cpp	Use Argument::hasAttribute and AttributeList::ReturnIndex more	2017-04-28 18:37:16 +00:00
AArch64FrameLowering.cpp	Move size and alignment information of regclass to TargetRegisterInfo	2017-04-24 18:55:33 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def
AArch64InstrAtomics.td	AArch64: lower "fence singlethread" to a pure compiler barrier.	2017-04-20 21:57:45 +00:00
AArch64InstrFormats.td	[globalisel][tablegen] Revise API for ComplexPattern operands to improve flexibility.	2017-04-22 15:11:04 +00:00
AArch64InstrInfo.cpp	Move size and alignment information of regclass to TargetRegisterInfo	2017-04-24 18:55:33 +00:00
AArch64InstrInfo.h	Re-commit r301040 "X86: Don't emit zero-byte functions on Windows"	2017-04-21 21:48:41 +00:00
AArch64InstrInfo.td	[AARCH64][NEON] Add support for ISD::ABS lowering	2017-05-08 10:25:18 +00:00
AArch64InstructionSelector.cpp	[globalisel][tablegen] Compute available feature bits correctly.	2017-04-29 17:30:09 +00:00
AArch64ISelDAGToDAG.cpp	[SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits	2017-04-28 05:31:46 +00:00
AArch64ISelLowering.cpp	[AARCH64][NEON] Add support for ISD::ABS lowering	2017-05-08 10:25:18 +00:00
AArch64ISelLowering.h	[SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and simplifyDemandedBits	2017-04-28 05:31:46 +00:00
AArch64LegalizerInfo.cpp	GlobalISel: constrain G_INSERT to inserting just one value per instruction.	2017-03-03 23:05:47 +00:00
AArch64LegalizerInfo.h
AArch64LoadStoreOptimizer.cpp	[AArch64] Use alias analysis in the load/store optimization pass.	2017-03-17 14:19:55 +00:00
AArch64MachineFunctionInfo.h
AArch64MacroFusion.cpp	[AArch64] Simplify MacroFusion	2017-04-11 19:13:11 +00:00
AArch64MacroFusion.h
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp
AArch64RedundantCopyElimination.cpp	[AArch64][Redundant Copy Elim] Add support for CMN and shifted imm.	2017-03-06 21:20:00 +00:00
AArch64RegisterBankInfo.cpp	[RegisterBankInfo] Uniquely allocate instruction mapping.	2017-05-05 22:48:22 +00:00
AArch64RegisterBankInfo.h	[RegisterBankInfo] Uniquely allocate instruction mapping.	2017-05-05 22:48:22 +00:00
AArch64RegisterBanks.td
AArch64RegisterInfo.cpp
AArch64RegisterInfo.h
AArch64RegisterInfo.td
AArch64SchedA53.td	[MachineScheduler] Reference the correct header.	2017-03-26 21:27:21 +00:00
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedFalkor.td	[AArch64][Falkor] Fix number of microops for WriteSTIdx missed in r300892.	2017-04-21 13:37:01 +00:00
AArch64SchedFalkorDetails.td	[AArch64][Falkor] Refine modeling of store-release exclusive instructions.	2017-04-21 14:58:32 +00:00
AArch64SchedFalkorWriteRes.td	[AArch64][Falkor] Refine modeling of store-release exclusive instructions.	2017-04-21 14:58:32 +00:00
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedM1.td
AArch64SchedThunderX2T99.td	[AArch64] Vulcan is now ThunderXT99	2017-03-07 19:42:40 +00:00
AArch64SchedThunderX.td	[AArch64] Vulcan is now ThunderXT99	2017-03-07 19:42:40 +00:00
AArch64Schedule.td
AArch64SelectionDAGInfo.cpp	[AArch64] Drive-by cleanup, make this code shorter. NFCI.	2017-03-22 23:37:58 +00:00
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp
AArch64Subtarget.cpp	[AArch64] Move GISel accessor initialization from TargetMachine to Subtarget.	2017-05-01 21:53:19 +00:00
AArch64Subtarget.h	[globalisel][tablegen] Compute available feature bits correctly.	2017-04-29 17:30:09 +00:00
AArch64SystemOperands.td
AArch64TargetMachine.cpp	[AArch64] Remove AArch64AddressTypePromotion pass	2017-05-05 16:05:41 +00:00
AArch64TargetMachine.h	[globalisel][tablegen] Move <Target>InstructionSelector declarations to anonymous namespaces	2017-04-06 09:49:34 +00:00
AArch64TargetObjectFile.cpp
AArch64TargetObjectFile.h
AArch64TargetTransformInfo.cpp	[SystemZ] TargetTransformInfo cost functions implemented.	2017-04-12 11:49:08 +00:00
AArch64TargetTransformInfo.h	[SystemZ] TargetTransformInfo cost functions implemented.	2017-04-12 11:49:08 +00:00
AArch64VectorByElementOpt.cpp
CMakeLists.txt	[AArch64] Remove AArch64AddressTypePromotion pass	2017-05-05 16:05:41 +00:00
LLVMBuild.txt