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llvm-mirror/test/CodeGen/SPARC/register-clobber.ll
James Y Knight 2b851af232 Check for register clobbers when merging a vreg live range with a
reserved physreg in RegisterCoalescer.

Previously, we only checked for clobbers when merging into a READ of
the physreg, but not when merging from a WRITE to the physreg.

Differential Revision: https://reviews.llvm.org/D28527

llvm-svn: 291942
2017-01-13 19:08:36 +00:00

36 lines
1002 B
LLVM

; RUN: llc -march=sparc < %s | FileCheck %s
;; Verify that g1 (the output of first asm) is properly understood to
;; be clobbered by the call instruction, and moved out of the way
;; before it. (NOTE: remember delay slot; mov executes before call)
; CHECK-LABEL: test1:
; CHECK: ta 9
; CHECK: call dosomething
; CHECK: mov %g1, %i0
define i32 @test1() nounwind {
entry:
%0 = tail call i32 asm sideeffect "ta $1", "={r1},i"(i32 9) nounwind
tail call void @dosomething() nounwind
ret i32 %0
}
;; Also check using the value.
; CHECK-LABEL: test2:
; CHECK: ta 9
; CHECK: call dosomething
; CHECK: mov %g1, %i0
; CHECK: mov %i0, %g1
; CHECK: ta 10
define void @test2() local_unnamed_addr nounwind {
entry:
%0 = tail call i32 asm sideeffect "ta $1", "={r1},i"(i32 9) nounwind
tail call void @dosomething() nounwind
tail call void asm sideeffect "ta $0", "i,{r1}"(i32 10, i32 %0) nounwind
ret void
}
declare void @dosomething() local_unnamed_addr nounwind