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6f27d8c6b3
Summary: MCTargetDesc/AMDGPUMCTargetDesc.h contains enums for all the instuction and register defintions, which are huge so we only want to include them where needed. This will also make it easier if we want to split the R600 and GCN definitions into separate tablegenerated files. I was unable to remove AMDGPUMCTargetDesc.h from SIMachineFunctionInfo.h because it uses some enums from the header to initialize default values for the SIMachineFunction class, so I ended up having to remove includes of SIMachineFunctionInfo.h from headers too. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: MatzeB, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D46272 llvm-svn: 332930
112 lines
3.5 KiB
C++
112 lines
3.5 KiB
C++
//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// R600 implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "R600RegisterInfo.h"
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#include "AMDGPUTargetMachine.h"
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#include "R600Defines.h"
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#include "R600InstrInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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using namespace llvm;
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R600RegisterInfo::R600RegisterInfo() : AMDGPURegisterInfo() {
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RCW.RegWeight = 0;
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RCW.WeightLimit = 0;
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}
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BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
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const R600InstrInfo *TII = ST.getInstrInfo();
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reserveRegisterTuples(Reserved, AMDGPU::ZERO);
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reserveRegisterTuples(Reserved, AMDGPU::HALF);
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reserveRegisterTuples(Reserved, AMDGPU::ONE);
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reserveRegisterTuples(Reserved, AMDGPU::ONE_INT);
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reserveRegisterTuples(Reserved, AMDGPU::NEG_HALF);
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reserveRegisterTuples(Reserved, AMDGPU::NEG_ONE);
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reserveRegisterTuples(Reserved, AMDGPU::PV_X);
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reserveRegisterTuples(Reserved, AMDGPU::ALU_LITERAL_X);
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reserveRegisterTuples(Reserved, AMDGPU::ALU_CONST);
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reserveRegisterTuples(Reserved, AMDGPU::PREDICATE_BIT);
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reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_OFF);
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reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ZERO);
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reserveRegisterTuples(Reserved, AMDGPU::PRED_SEL_ONE);
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reserveRegisterTuples(Reserved, AMDGPU::INDIRECT_BASE_ADDR);
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for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
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E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) {
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reserveRegisterTuples(Reserved, *I);
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}
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TII->reserveIndirectRegisters(Reserved, MF, *this);
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return Reserved;
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}
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// Dummy to not crash RegisterClassInfo.
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static const MCPhysReg CalleeSavedReg = AMDGPU::NoRegister;
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const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
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const MachineFunction *) const {
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return &CalleeSavedReg;
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}
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unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return AMDGPU::NoRegister;
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}
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unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
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return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
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}
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unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
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return GET_REG_INDEX(getEncodingValue(Reg));
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}
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const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
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MVT VT) const {
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switch(VT.SimpleTy) {
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default:
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case MVT::i32: return &AMDGPU::R600_TReg32RegClass;
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}
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}
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const RegClassWeight &R600RegisterInfo::getRegClassWeight(
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const TargetRegisterClass *RC) const {
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return RCW;
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}
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bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
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assert(!TargetRegisterInfo::isVirtualRegister(Reg));
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switch (Reg) {
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case AMDGPU::OQAP:
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case AMDGPU::OQBP:
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case AMDGPU::AR_X:
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return false;
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default:
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return true;
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}
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}
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void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
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int SPAdj,
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unsigned FIOperandNum,
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RegScavenger *RS) const {
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llvm_unreachable("Subroutines not supported yet");
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}
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