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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 14:33:02 +02:00
llvm-mirror/include
Dan Gohman 790659c0d6 Fix FastISel's assumption that i1 values are always zero-extended
by inserting explicit zero extensions where necessary. Included
is a testcase where SelectionDAG produces a virtual register
holding an i1 value which FastISel previously mistakenly assumed
to be zero-extended.

llvm-svn: 66941
2009-03-13 20:42:20 +00:00
..
llvm Fix FastISel's assumption that i1 values are always zero-extended 2009-03-13 20:42:20 +00:00
llvm-c It makes no sense to have a ODR version of common 2009-03-11 20:14:15 +00:00