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daef1ea7bc
LowerVECTOR_SHUFFLE needs to decide whether to pass a vector shuffle off to the TableGen-generated matching code, and it does this by testing the same predicates used by the TableGen files. Unfortunately, when we added new P8Altivec-only predicates, we started universally testing them in LowerVECTOR_SHUFFLE, and if then matched when targeting a system prior to a P8, we'd end up with a selection failure. llvm-svn: 246675
29 lines
851 B
LLVM
29 lines
851 B
LLVM
; RUN: llc < %s | FileCheck %s
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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; Function Attrs: nounwind
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define <2 x i32> @test1(<4 x i32> %wide.vec) #0 {
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entry:
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%strided.vec = shufflevector <4 x i32> %wide.vec, <4 x i32> undef, <2 x i32> <i32 0, i32 2>
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ret <2 x i32> %strided.vec
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; CHECK-LABEL: @test1
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; CHECK: vsldoi 2, 2, 2, 12
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; CHECK: blr
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}
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; Function Attrs: nounwind
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define <16 x i8> @test2(<16 x i8> %wide.vec) #0 {
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entry:
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%strided.vec = shufflevector <16 x i8> %wide.vec, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 8, i32 9, i32 10, i32 11>
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ret <16 x i8> %strided.vec
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; CHECK-LABEL: @test2
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; CHECK: vsldoi 2, 2, 2, 12
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; CHECK: blr
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}
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attributes #0 = { nounwind "target-cpu"="pwr7" }
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