mirror of
https://github.com/RPCS3/llvm-mirror.git
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4316b2ca5f
Extended avx512_icmp_packed multiclass by masking versions.
Added avx512_icmp_packed_rmb multiclass for embedded broadcast versions.
Added corresponding _vl multiclasses.
Added encoding tests for CPCMP{EQ|GT}* instructions.
Add more fields for X86VectorVTInfo.
Added AVX512VLVectorVTInfo that include X86VectorVTInfo for 512/256/128-bit versions
Differential Revision: http://reviews.llvm.org/D5024
llvm-svn: 216383
871 lines
28 KiB
C++
871 lines
28 KiB
C++
//===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the X86 Disassembler Emitter.
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// It contains the implementation of the disassembler tables.
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// Documentation for the disassembler emitter in general can be found in
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// X86DisasemblerEmitter.h.
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//
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//===----------------------------------------------------------------------===//
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#include "X86DisassemblerTables.h"
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#include "X86DisassemblerShared.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/Format.h"
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#include <map>
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using namespace llvm;
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using namespace X86Disassembler;
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/// stringForContext - Returns a string containing the name of a particular
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/// InstructionContext, usually for diagnostic purposes.
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///
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/// @param insnContext - The instruction class to transform to a string.
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/// @return - A statically-allocated string constant that contains the
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/// name of the instruction class.
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static inline const char* stringForContext(InstructionContext insnContext) {
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switch (insnContext) {
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default:
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llvm_unreachable("Unhandled instruction class");
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#define ENUM_ENTRY(n, r, d) case n: return #n; break;
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#define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
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ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
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ENUM_ENTRY(n##_KZ_B, r, d)
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INSTRUCTION_CONTEXTS
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#undef ENUM_ENTRY
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#undef ENUM_ENTRY_K_B
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}
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}
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/// stringForOperandType - Like stringForContext, but for OperandTypes.
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static inline const char* stringForOperandType(OperandType type) {
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switch (type) {
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default:
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llvm_unreachable("Unhandled type");
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#define ENUM_ENTRY(i, d) case i: return #i;
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TYPES
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#undef ENUM_ENTRY
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}
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}
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/// stringForOperandEncoding - like stringForContext, but for
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/// OperandEncodings.
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static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
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switch (encoding) {
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default:
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llvm_unreachable("Unhandled encoding");
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#define ENUM_ENTRY(i, d) case i: return #i;
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ENCODINGS
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#undef ENUM_ENTRY
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}
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}
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/// inheritsFrom - Indicates whether all instructions in one class also belong
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/// to another class.
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///
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/// @param child - The class that may be the subset
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/// @param parent - The class that may be the superset
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/// @return - True if child is a subset of parent, false otherwise.
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static inline bool inheritsFrom(InstructionContext child,
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InstructionContext parent,
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bool VEX_LIG = false) {
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if (child == parent)
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return true;
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switch (parent) {
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case IC:
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return(inheritsFrom(child, IC_64BIT) ||
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inheritsFrom(child, IC_OPSIZE) ||
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inheritsFrom(child, IC_ADSIZE) ||
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inheritsFrom(child, IC_XD) ||
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inheritsFrom(child, IC_XS));
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case IC_64BIT:
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return(inheritsFrom(child, IC_64BIT_REXW) ||
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inheritsFrom(child, IC_64BIT_OPSIZE) ||
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inheritsFrom(child, IC_64BIT_ADSIZE) ||
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inheritsFrom(child, IC_64BIT_XD) ||
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inheritsFrom(child, IC_64BIT_XS));
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case IC_OPSIZE:
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return inheritsFrom(child, IC_64BIT_OPSIZE);
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case IC_ADSIZE:
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case IC_64BIT_ADSIZE:
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return false;
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case IC_XD:
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return inheritsFrom(child, IC_64BIT_XD);
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case IC_XS:
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return inheritsFrom(child, IC_64BIT_XS);
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case IC_XD_OPSIZE:
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return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
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case IC_XS_OPSIZE:
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return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
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case IC_64BIT_REXW:
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return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
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inheritsFrom(child, IC_64BIT_REXW_XD) ||
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inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
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case IC_64BIT_OPSIZE:
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return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
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case IC_64BIT_XD:
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return(inheritsFrom(child, IC_64BIT_REXW_XD));
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case IC_64BIT_XS:
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return(inheritsFrom(child, IC_64BIT_REXW_XS));
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case IC_64BIT_XD_OPSIZE:
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case IC_64BIT_XS_OPSIZE:
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return false;
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case IC_64BIT_REXW_XD:
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case IC_64BIT_REXW_XS:
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case IC_64BIT_REXW_OPSIZE:
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return false;
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case IC_VEX:
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return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
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inheritsFrom(child, IC_VEX_W) ||
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(VEX_LIG && inheritsFrom(child, IC_VEX_L));
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case IC_VEX_XS:
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return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
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inheritsFrom(child, IC_VEX_W_XS) ||
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(VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
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case IC_VEX_XD:
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return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
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inheritsFrom(child, IC_VEX_W_XD) ||
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(VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
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case IC_VEX_OPSIZE:
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return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
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inheritsFrom(child, IC_VEX_W_OPSIZE) ||
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(VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
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case IC_VEX_W:
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return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
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case IC_VEX_W_XS:
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return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
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case IC_VEX_W_XD:
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return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
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case IC_VEX_W_OPSIZE:
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return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
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case IC_VEX_L:
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return inheritsFrom(child, IC_VEX_L_W);
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case IC_VEX_L_XS:
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return inheritsFrom(child, IC_VEX_L_W_XS);
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case IC_VEX_L_XD:
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return inheritsFrom(child, IC_VEX_L_W_XD);
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case IC_VEX_L_OPSIZE:
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return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
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case IC_VEX_L_W:
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case IC_VEX_L_W_XS:
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case IC_VEX_L_W_XD:
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case IC_VEX_L_W_OPSIZE:
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return false;
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case IC_EVEX:
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return inheritsFrom(child, IC_EVEX_W) ||
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inheritsFrom(child, IC_EVEX_L_W);
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case IC_EVEX_XS:
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return inheritsFrom(child, IC_EVEX_W_XS) ||
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inheritsFrom(child, IC_EVEX_L_W_XS);
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case IC_EVEX_XD:
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return inheritsFrom(child, IC_EVEX_W_XD) ||
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inheritsFrom(child, IC_EVEX_L_W_XD);
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case IC_EVEX_OPSIZE:
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return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
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inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
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case IC_EVEX_W:
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case IC_EVEX_W_XS:
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case IC_EVEX_W_XD:
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case IC_EVEX_W_OPSIZE:
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return false;
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case IC_EVEX_L:
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case IC_EVEX_L_XS:
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case IC_EVEX_L_XD:
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case IC_EVEX_L_OPSIZE:
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return false;
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case IC_EVEX_L_W:
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case IC_EVEX_L_W_XS:
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case IC_EVEX_L_W_XD:
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case IC_EVEX_L_W_OPSIZE:
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return false;
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case IC_EVEX_L2:
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case IC_EVEX_L2_XS:
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case IC_EVEX_L2_XD:
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case IC_EVEX_L2_OPSIZE:
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return false;
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case IC_EVEX_L2_W:
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case IC_EVEX_L2_W_XS:
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case IC_EVEX_L2_W_XD:
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case IC_EVEX_L2_W_OPSIZE:
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return false;
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case IC_EVEX_K:
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return inheritsFrom(child, IC_EVEX_W_K) ||
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inheritsFrom(child, IC_EVEX_L_W_K);
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case IC_EVEX_XS_K:
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return inheritsFrom(child, IC_EVEX_W_XS_K) ||
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inheritsFrom(child, IC_EVEX_L_W_XS_K);
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case IC_EVEX_XD_K:
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return inheritsFrom(child, IC_EVEX_W_XD_K) ||
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inheritsFrom(child, IC_EVEX_L_W_XD_K);
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case IC_EVEX_K_B:
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case IC_EVEX_KZ:
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return false;
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case IC_EVEX_XS_KZ:
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return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
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inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
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case IC_EVEX_XD_KZ:
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return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
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inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
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case IC_EVEX_KZ_B:
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case IC_EVEX_OPSIZE_K:
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case IC_EVEX_OPSIZE_B:
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case IC_EVEX_OPSIZE_K_B:
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case IC_EVEX_OPSIZE_KZ:
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return false;
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case IC_EVEX_W_K:
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case IC_EVEX_W_XS_K:
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case IC_EVEX_W_XD_K:
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case IC_EVEX_W_OPSIZE_K:
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case IC_EVEX_W_OPSIZE_B:
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case IC_EVEX_W_OPSIZE_K_B:
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return false;
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case IC_EVEX_L_K:
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case IC_EVEX_L_XS_K:
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case IC_EVEX_L_XD_K:
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case IC_EVEX_L_OPSIZE_K:
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case IC_EVEX_L_OPSIZE_B:
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case IC_EVEX_L_OPSIZE_K_B:
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return false;
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case IC_EVEX_W_KZ:
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case IC_EVEX_W_XS_KZ:
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case IC_EVEX_W_XD_KZ:
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case IC_EVEX_W_OPSIZE_KZ:
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return false;
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case IC_EVEX_L_KZ:
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case IC_EVEX_L_XS_KZ:
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case IC_EVEX_L_XD_KZ:
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case IC_EVEX_L_OPSIZE_KZ:
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return false;
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case IC_EVEX_L_W_K:
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case IC_EVEX_L_W_XS_K:
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case IC_EVEX_L_W_XD_K:
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case IC_EVEX_L_W_OPSIZE_K:
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case IC_EVEX_L_W_OPSIZE_B:
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case IC_EVEX_L_W_OPSIZE_K_B:
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case IC_EVEX_L_W_KZ:
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case IC_EVEX_L_W_XS_KZ:
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case IC_EVEX_L_W_XD_KZ:
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case IC_EVEX_L_W_OPSIZE_KZ:
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return false;
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case IC_EVEX_L2_K:
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case IC_EVEX_L2_B:
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case IC_EVEX_L2_K_B:
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case IC_EVEX_L2_KZ_B:
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case IC_EVEX_L2_XS_K:
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case IC_EVEX_L2_XS_B:
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case IC_EVEX_L2_XD_B:
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case IC_EVEX_L2_XD_K:
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case IC_EVEX_L2_OPSIZE_K:
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case IC_EVEX_L2_OPSIZE_B:
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case IC_EVEX_L2_OPSIZE_K_B:
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case IC_EVEX_L2_KZ:
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case IC_EVEX_L2_XS_KZ:
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case IC_EVEX_L2_XD_KZ:
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case IC_EVEX_L2_OPSIZE_KZ:
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case IC_EVEX_L2_OPSIZE_KZ_B:
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return false;
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case IC_EVEX_L2_W_K:
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case IC_EVEX_L2_W_B:
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case IC_EVEX_L2_W_XS_K:
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case IC_EVEX_L2_W_XD_K:
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case IC_EVEX_L2_W_XD_B:
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case IC_EVEX_L2_W_OPSIZE_K:
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case IC_EVEX_L2_W_OPSIZE_B:
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case IC_EVEX_L2_W_OPSIZE_K_B:
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case IC_EVEX_L2_W_KZ:
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case IC_EVEX_L2_W_XS_KZ:
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case IC_EVEX_L2_W_XD_KZ:
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case IC_EVEX_L2_W_OPSIZE_KZ:
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case IC_EVEX_L2_W_OPSIZE_KZ_B:
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return false;
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default:
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errs() << "Unknown instruction class: " <<
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stringForContext((InstructionContext)parent) << "\n";
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llvm_unreachable("Unknown instruction class");
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}
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}
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/// outranks - Indicates whether, if an instruction has two different applicable
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/// classes, which class should be preferred when performing decode. This
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/// imposes a total ordering (ties are resolved toward "lower")
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///
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/// @param upper - The class that may be preferable
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/// @param lower - The class that may be less preferable
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/// @return - True if upper is to be preferred, false otherwise.
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static inline bool outranks(InstructionContext upper,
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InstructionContext lower) {
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assert(upper < IC_max);
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assert(lower < IC_max);
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#define ENUM_ENTRY(n, r, d) r,
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#define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
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ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
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ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
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static int ranks[IC_max] = {
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INSTRUCTION_CONTEXTS
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};
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#undef ENUM_ENTRY
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#undef ENUM_ENTRY_K_B
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return (ranks[upper] > ranks[lower]);
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}
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/// getDecisionType - Determines whether a ModRM decision with 255 entries can
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/// be compacted by eliminating redundant information.
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///
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/// @param decision - The decision to be compacted.
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/// @return - The compactest available representation for the decision.
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static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
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bool satisfiesOneEntry = true;
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bool satisfiesSplitRM = true;
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bool satisfiesSplitReg = true;
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bool satisfiesSplitMisc = true;
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for (unsigned index = 0; index < 256; ++index) {
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if (decision.instructionIDs[index] != decision.instructionIDs[0])
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satisfiesOneEntry = false;
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if (((index & 0xc0) == 0xc0) &&
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(decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
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satisfiesSplitRM = false;
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if (((index & 0xc0) != 0xc0) &&
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(decision.instructionIDs[index] != decision.instructionIDs[0x00]))
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satisfiesSplitRM = false;
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if (((index & 0xc0) == 0xc0) &&
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(decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
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satisfiesSplitReg = false;
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if (((index & 0xc0) != 0xc0) &&
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(decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
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satisfiesSplitMisc = false;
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}
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if (satisfiesOneEntry)
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return MODRM_ONEENTRY;
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if (satisfiesSplitRM)
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return MODRM_SPLITRM;
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if (satisfiesSplitReg && satisfiesSplitMisc)
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return MODRM_SPLITREG;
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if (satisfiesSplitMisc)
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return MODRM_SPLITMISC;
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return MODRM_FULL;
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}
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/// stringForDecisionType - Returns a statically-allocated string corresponding
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/// to a particular decision type.
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///
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/// @param dt - The decision type.
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/// @return - A pointer to the statically-allocated string (e.g.,
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/// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
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static const char* stringForDecisionType(ModRMDecisionType dt) {
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#define ENUM_ENTRY(n) case n: return #n;
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switch (dt) {
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default:
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llvm_unreachable("Unknown decision type");
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MODRMTYPES
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};
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#undef ENUM_ENTRY
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}
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DisassemblerTables::DisassemblerTables() {
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unsigned i;
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for (i = 0; i < array_lengthof(Tables); i++) {
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Tables[i] = new ContextDecision;
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memset(Tables[i], 0, sizeof(ContextDecision));
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}
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HasConflicts = false;
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}
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DisassemblerTables::~DisassemblerTables() {
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unsigned i;
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for (i = 0; i < array_lengthof(Tables); i++)
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delete Tables[i];
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}
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void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
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unsigned &i1, unsigned &i2,
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unsigned &ModRMTableNum,
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ModRMDecision &decision) const {
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static uint32_t sTableNumber = 0;
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static uint32_t sEntryNumber = 1;
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ModRMDecisionType dt = getDecisionType(decision);
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if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
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{
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o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
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i2++;
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o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
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o2.indent(i2) << 0 << " /* EmptyTable */\n";
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i2--;
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o2.indent(i2) << "}";
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return;
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}
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std::vector<unsigned> ModRMDecision;
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switch (dt) {
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default:
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llvm_unreachable("Unknown decision type");
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case MODRM_ONEENTRY:
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ModRMDecision.push_back(decision.instructionIDs[0]);
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break;
|
|
case MODRM_SPLITRM:
|
|
ModRMDecision.push_back(decision.instructionIDs[0x00]);
|
|
ModRMDecision.push_back(decision.instructionIDs[0xc0]);
|
|
break;
|
|
case MODRM_SPLITREG:
|
|
for (unsigned index = 0; index < 64; index += 8)
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
for (unsigned index = 0xc0; index < 256; index += 8)
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
break;
|
|
case MODRM_SPLITMISC:
|
|
for (unsigned index = 0; index < 64; index += 8)
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
for (unsigned index = 0xc0; index < 256; ++index)
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
break;
|
|
case MODRM_FULL:
|
|
for (unsigned index = 0; index < 256; ++index)
|
|
ModRMDecision.push_back(decision.instructionIDs[index]);
|
|
break;
|
|
}
|
|
|
|
unsigned &EntryNumber = ModRMTable[ModRMDecision];
|
|
if (EntryNumber == 0) {
|
|
EntryNumber = ModRMTableNum;
|
|
|
|
ModRMTableNum += ModRMDecision.size();
|
|
o1 << "/* Table" << EntryNumber << " */\n";
|
|
i1++;
|
|
for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
|
|
E = ModRMDecision.end(); I != E; ++I) {
|
|
o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
|
|
<< InstructionSpecifiers[*I].name << " */\n";
|
|
}
|
|
i1--;
|
|
}
|
|
|
|
o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
|
|
i2++;
|
|
|
|
o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
|
|
o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
|
|
|
|
i2--;
|
|
o2.indent(i2) << "}";
|
|
|
|
switch (dt) {
|
|
default:
|
|
llvm_unreachable("Unknown decision type");
|
|
case MODRM_ONEENTRY:
|
|
sEntryNumber += 1;
|
|
break;
|
|
case MODRM_SPLITRM:
|
|
sEntryNumber += 2;
|
|
break;
|
|
case MODRM_SPLITREG:
|
|
sEntryNumber += 16;
|
|
break;
|
|
case MODRM_SPLITMISC:
|
|
sEntryNumber += 8 + 64;
|
|
break;
|
|
case MODRM_FULL:
|
|
sEntryNumber += 256;
|
|
break;
|
|
}
|
|
|
|
// We assume that the index can fit into uint16_t.
|
|
assert(sEntryNumber < 65536U &&
|
|
"Index into ModRMDecision is too large for uint16_t!");
|
|
|
|
++sTableNumber;
|
|
}
|
|
|
|
void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
|
|
unsigned &i1, unsigned &i2,
|
|
unsigned &ModRMTableNum,
|
|
OpcodeDecision &decision) const {
|
|
o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
|
|
i2++;
|
|
o2.indent(i2) << "{" << "\n";
|
|
i2++;
|
|
|
|
for (unsigned index = 0; index < 256; ++index) {
|
|
o2.indent(i2);
|
|
|
|
o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
|
|
|
|
emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
|
|
decision.modRMDecisions[index]);
|
|
|
|
if (index < 255)
|
|
o2 << ",";
|
|
|
|
o2 << "\n";
|
|
}
|
|
|
|
i2--;
|
|
o2.indent(i2) << "}" << "\n";
|
|
i2--;
|
|
o2.indent(i2) << "}" << "\n";
|
|
}
|
|
|
|
void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
|
|
unsigned &i1, unsigned &i2,
|
|
unsigned &ModRMTableNum,
|
|
ContextDecision &decision,
|
|
const char* name) const {
|
|
o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
|
|
i2++;
|
|
o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
|
|
i2++;
|
|
|
|
for (unsigned index = 0; index < IC_max; ++index) {
|
|
o2.indent(i2) << "/* ";
|
|
o2 << stringForContext((InstructionContext)index);
|
|
o2 << " */";
|
|
o2 << "\n";
|
|
|
|
emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
|
|
decision.opcodeDecisions[index]);
|
|
|
|
if (index + 1 < IC_max)
|
|
o2 << ", ";
|
|
}
|
|
|
|
i2--;
|
|
o2.indent(i2) << "}" << "\n";
|
|
i2--;
|
|
o2.indent(i2) << "};" << "\n";
|
|
}
|
|
|
|
void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
|
|
unsigned &i) const {
|
|
unsigned NumInstructions = InstructionSpecifiers.size();
|
|
|
|
o << "static const struct OperandSpecifier x86OperandSets[]["
|
|
<< X86_MAX_OPERANDS << "] = {\n";
|
|
|
|
typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
|
|
std::map<OperandListTy, unsigned> OperandSets;
|
|
|
|
unsigned OperandSetNum = 0;
|
|
for (unsigned Index = 0; Index < NumInstructions; ++Index) {
|
|
OperandListTy OperandList;
|
|
|
|
for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
|
|
++OperandIndex) {
|
|
const char *Encoding =
|
|
stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
|
|
.operands[OperandIndex].encoding);
|
|
const char *Type =
|
|
stringForOperandType((OperandType)InstructionSpecifiers[Index]
|
|
.operands[OperandIndex].type);
|
|
OperandList.push_back(std::make_pair(Encoding, Type));
|
|
}
|
|
unsigned &N = OperandSets[OperandList];
|
|
if (N != 0) continue;
|
|
|
|
N = ++OperandSetNum;
|
|
|
|
o << " { /* " << (OperandSetNum - 1) << " */\n";
|
|
for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
|
|
o << " { " << OperandList[i].first << ", "
|
|
<< OperandList[i].second << " },\n";
|
|
}
|
|
o << " },\n";
|
|
}
|
|
o << "};" << "\n\n";
|
|
|
|
o.indent(i * 2) << "static const struct InstructionSpecifier ";
|
|
o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
|
|
|
|
i++;
|
|
|
|
for (unsigned index = 0; index < NumInstructions; ++index) {
|
|
o.indent(i * 2) << "{ /* " << index << " */" << "\n";
|
|
i++;
|
|
|
|
OperandListTy OperandList;
|
|
for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
|
|
++OperandIndex) {
|
|
const char *Encoding =
|
|
stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
|
|
.operands[OperandIndex].encoding);
|
|
const char *Type =
|
|
stringForOperandType((OperandType)InstructionSpecifiers[index]
|
|
.operands[OperandIndex].type);
|
|
OperandList.push_back(std::make_pair(Encoding, Type));
|
|
}
|
|
o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
|
|
|
|
o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
|
|
o << "\n";
|
|
|
|
i--;
|
|
o.indent(i * 2) << "}";
|
|
|
|
if (index + 1 < NumInstructions)
|
|
o << ",";
|
|
|
|
o << "\n";
|
|
}
|
|
|
|
i--;
|
|
o.indent(i * 2) << "};" << "\n";
|
|
}
|
|
|
|
void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
|
|
const unsigned int tableSize = 16384;
|
|
o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
|
|
"[" << tableSize << "] = {\n";
|
|
i++;
|
|
|
|
for (unsigned index = 0; index < tableSize; ++index) {
|
|
o.indent(i * 2);
|
|
|
|
if (index & ATTR_EVEX) {
|
|
o << "IC_EVEX";
|
|
if (index & ATTR_EVEXL2)
|
|
o << "_L2";
|
|
else if (index & ATTR_EVEXL)
|
|
o << "_L";
|
|
if (index & ATTR_REXW)
|
|
o << "_W";
|
|
if (index & ATTR_OPSIZE)
|
|
o << "_OPSIZE";
|
|
else if (index & ATTR_XD)
|
|
o << "_XD";
|
|
else if (index & ATTR_XS)
|
|
o << "_XS";
|
|
if (index & ATTR_EVEXKZ)
|
|
o << "_KZ";
|
|
else if (index & ATTR_EVEXK)
|
|
o << "_K";
|
|
if (index & ATTR_EVEXB)
|
|
o << "_B";
|
|
}
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
|
|
o << "IC_VEX_L_W_OPSIZE";
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
|
|
o << "IC_VEX_L_W_XD";
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
|
|
o << "IC_VEX_L_W_XS";
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
|
|
o << "IC_VEX_L_W";
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
|
|
o << "IC_VEX_L_OPSIZE";
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_XD))
|
|
o << "IC_VEX_L_XD";
|
|
else if ((index & ATTR_VEXL) && (index & ATTR_XS))
|
|
o << "IC_VEX_L_XS";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
|
|
o << "IC_VEX_W_OPSIZE";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
|
|
o << "IC_VEX_W_XD";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
|
|
o << "IC_VEX_W_XS";
|
|
else if (index & ATTR_VEXL)
|
|
o << "IC_VEX_L";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_REXW))
|
|
o << "IC_VEX_W";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
|
|
o << "IC_VEX_OPSIZE";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_XD))
|
|
o << "IC_VEX_XD";
|
|
else if ((index & ATTR_VEX) && (index & ATTR_XS))
|
|
o << "IC_VEX_XS";
|
|
else if (index & ATTR_VEX)
|
|
o << "IC_VEX";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
|
|
o << "IC_64BIT_REXW_XS";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
|
|
o << "IC_64BIT_REXW_XD";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
|
|
(index & ATTR_OPSIZE))
|
|
o << "IC_64BIT_REXW_OPSIZE";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
|
|
o << "IC_64BIT_XD_OPSIZE";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
|
|
o << "IC_64BIT_XS_OPSIZE";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XS))
|
|
o << "IC_64BIT_XS";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_XD))
|
|
o << "IC_64BIT_XD";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
|
|
o << "IC_64BIT_OPSIZE";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
|
|
o << "IC_64BIT_ADSIZE";
|
|
else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
|
|
o << "IC_64BIT_REXW";
|
|
else if ((index & ATTR_64BIT))
|
|
o << "IC_64BIT";
|
|
else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
|
|
o << "IC_XS_OPSIZE";
|
|
else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
|
|
o << "IC_XD_OPSIZE";
|
|
else if (index & ATTR_XS)
|
|
o << "IC_XS";
|
|
else if (index & ATTR_XD)
|
|
o << "IC_XD";
|
|
else if (index & ATTR_OPSIZE)
|
|
o << "IC_OPSIZE";
|
|
else if (index & ATTR_ADSIZE)
|
|
o << "IC_ADSIZE";
|
|
else
|
|
o << "IC";
|
|
|
|
if (index < tableSize - 1)
|
|
o << ",";
|
|
else
|
|
o << " ";
|
|
|
|
o << " /* " << index << " */";
|
|
|
|
o << "\n";
|
|
}
|
|
|
|
i--;
|
|
o.indent(i * 2) << "};" << "\n";
|
|
}
|
|
|
|
void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
|
|
unsigned &i1, unsigned &i2,
|
|
unsigned &ModRMTableNum) const {
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
|
|
emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
|
|
}
|
|
|
|
void DisassemblerTables::emit(raw_ostream &o) const {
|
|
unsigned i1 = 0;
|
|
unsigned i2 = 0;
|
|
|
|
std::string s1;
|
|
std::string s2;
|
|
|
|
raw_string_ostream o1(s1);
|
|
raw_string_ostream o2(s2);
|
|
|
|
emitInstructionInfo(o, i2);
|
|
o << "\n";
|
|
|
|
emitContextTable(o, i2);
|
|
o << "\n";
|
|
|
|
unsigned ModRMTableNum = 0;
|
|
|
|
o << "static const InstrUID modRMTable[] = {\n";
|
|
i1++;
|
|
std::vector<unsigned> EmptyTable(1, 0);
|
|
ModRMTable[EmptyTable] = ModRMTableNum;
|
|
ModRMTableNum += EmptyTable.size();
|
|
o1 << "/* EmptyTable */\n";
|
|
o1.indent(i1 * 2) << "0x0,\n";
|
|
i1--;
|
|
emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
|
|
|
|
o << o1.str();
|
|
o << " 0x0\n";
|
|
o << "};\n";
|
|
o << "\n";
|
|
o << o2.str();
|
|
o << "\n";
|
|
o << "\n";
|
|
}
|
|
|
|
void DisassemblerTables::setTableFields(ModRMDecision &decision,
|
|
const ModRMFilter &filter,
|
|
InstrUID uid,
|
|
uint8_t opcode) {
|
|
for (unsigned index = 0; index < 256; ++index) {
|
|
if (filter.accepts(index)) {
|
|
if (decision.instructionIDs[index] == uid)
|
|
continue;
|
|
|
|
if (decision.instructionIDs[index] != 0) {
|
|
InstructionSpecifier &newInfo =
|
|
InstructionSpecifiers[uid];
|
|
InstructionSpecifier &previousInfo =
|
|
InstructionSpecifiers[decision.instructionIDs[index]];
|
|
|
|
// Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
|
|
// presence of the AdSize prefix. However, the disassembler doesn't
|
|
// care about that difference in the instruction definition; it
|
|
// handles 16-bit vs. 32-bit addressing for itself based purely
|
|
// on the 0x67 prefix and the CPU mode. So there's no need to
|
|
// disambiguate between them; just let them conflict/coexist.
|
|
if (previousInfo.name + "_16" == newInfo.name)
|
|
continue;
|
|
|
|
if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
|
|
newInfo.name == "XCHG32ar" ||
|
|
newInfo.name == "XCHG32ar64" ||
|
|
newInfo.name == "XCHG64ar"))
|
|
continue; // special case for XCHG*ar and NOOP
|
|
|
|
if (outranks(previousInfo.insnContext, newInfo.insnContext))
|
|
continue;
|
|
|
|
if (previousInfo.insnContext == newInfo.insnContext) {
|
|
errs() << "Error: Primary decode conflict: ";
|
|
errs() << newInfo.name << " would overwrite " << previousInfo.name;
|
|
errs() << "\n";
|
|
errs() << "ModRM " << index << "\n";
|
|
errs() << "Opcode " << (uint16_t)opcode << "\n";
|
|
errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
|
|
HasConflicts = true;
|
|
}
|
|
}
|
|
|
|
decision.instructionIDs[index] = uid;
|
|
}
|
|
}
|
|
}
|
|
|
|
void DisassemblerTables::setTableFields(OpcodeType type,
|
|
InstructionContext insnContext,
|
|
uint8_t opcode,
|
|
const ModRMFilter &filter,
|
|
InstrUID uid,
|
|
bool is32bit,
|
|
bool ignoresVEX_L) {
|
|
ContextDecision &decision = *Tables[type];
|
|
|
|
for (unsigned index = 0; index < IC_max; ++index) {
|
|
if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
|
|
continue;
|
|
|
|
if (inheritsFrom((InstructionContext)index,
|
|
InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
|
|
setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],
|
|
filter,
|
|
uid,
|
|
opcode);
|
|
}
|
|
}
|