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8603948f83
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses. This removes most of the static_casting of the basic codegen classes everywhere, and tries to restrict the features visible on the wrong target. llvm-svn: 273652
50 lines
1.4 KiB
C++
50 lines
1.4 KiB
C++
//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Interface definition for R600RegisterInfo
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
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#define LLVM_LIB_TARGET_AMDGPU_R600REGISTERINFO_H
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#include "AMDGPURegisterInfo.h"
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namespace llvm {
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class AMDGPUSubtarget;
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struct R600RegisterInfo final : public AMDGPURegisterInfo {
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RegClassWeight RCW;
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R600RegisterInfo();
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BitVector getReservedRegs(const MachineFunction &MF) const override;
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/// \brief get the HW encoding for a register's channel.
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unsigned getHWRegChan(unsigned reg) const;
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unsigned getHWRegIndex(unsigned Reg) const;
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/// \brief get the register class of the specified type to use in the
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/// CFGStructurizer
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const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
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const RegClassWeight &
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getRegClassWeight(const TargetRegisterClass *RC) const override;
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// \returns true if \p Reg can be defined in one ALU caluse and used in another.
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bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
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};
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} // End namespace llvm
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#endif
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