Oliver Stannard 421ddae8b6 [AArch64] Add ARMv8.2-A FP16 vector instructions ... ARMv8.2-A adds 16-bit floating point versions of all existing SIMD floating-point instructions. This is an optional extension, so all of these instructions require the FeatureFullFP16 subtarget feature. Note that VFP without SIMD is not a valid combination for any version of ARMv8-A, but I have ensured that these instructions all depend on both FeatureNEON and FeatureFullFP16 for consistency. The ".2h" vector type specifier is now legal (for the scalar pairwise reduction instructions), so some unrelated tests have been modified as different error messages are emitted. This is not a problem as the invalid operands are still caught. llvm-svn: 255010		2015-12-08 12:16:10 +00:00
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AArch64AsmParser.cpp
CMakeLists.txt
LLVMBuild.txt
Makefile