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7994364d2f
The FPv4-SP floating-point unit is generally referred to as single-precision only, but it does have double-precision registers and load, store and GPR<->DPR move instructions which operate on them. This patch enables the use of these registers, the main advantage of which is that we now comply with the AAPCS-VFP calling convention. This partially reverts r209650, which added some AAPCS-VFP support, but did not handle return values or alignment of double arguments in registers. This patch also adds tests for Thumb2 code generation for floating-point instructions and intrinsics, which previously only existed for ARM. llvm-svn: 216172
25 lines
786 B
LLVM
25 lines
786 B
LLVM
; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM3
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-m4 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXM4
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 -march=thumb -mcpu=cortex-a8 | FileCheck %s -check-prefix=CHECK -check-prefix=CORTEXA8
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define float @foo(float %a, float %b) {
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entry:
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; CHECK-LABEL: foo:
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; CORTEXM3: bl ___mulsf3
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; CORTEXM4: vmul.f32 s
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; CORTEXA8: vmul.f32 d
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%0 = fmul float %a, %b
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ret float %0
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}
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define double @bar(double %a, double %b) {
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entry:
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; CHECK-LABEL: bar:
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%0 = fmul double %a, %b
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; CORTEXM3: bl ___muldf3
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; CORTEXM4: {{bl|b.w}} ___muldf3
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; CORTEXA8: vmul.f64 d
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ret double %0
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}
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