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d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
64 lines
1.8 KiB
LLVM
64 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
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define i32 @negate_nuw(i32 %x) {
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; CHECK-LABEL: negate_nuw:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%neg = sub nuw i32 0, %x
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ret i32 %neg
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}
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define <4 x i32> @negate_nuw_vec(<4 x i32> %x) {
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; CHECK-LABEL: negate_nuw_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%neg = sub nuw <4 x i32> zeroinitializer, %x
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ret <4 x i32> %neg
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}
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define i8 @negate_zero_or_minsigned_nsw(i8 %x) {
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; CHECK-LABEL: negate_zero_or_minsigned_nsw:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retq
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%signbit = and i8 %x, 128
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%neg = sub nsw i8 0, %signbit
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ret i8 %neg
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}
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define <4 x i32> @negate_zero_or_minsigned_nsw_vec(<4 x i32> %x) {
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; CHECK-LABEL: negate_zero_or_minsigned_nsw_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: xorps %xmm0, %xmm0
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; CHECK-NEXT: retq
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%signbit = shl <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
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%neg = sub nsw <4 x i32> zeroinitializer, %signbit
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ret <4 x i32> %neg
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}
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define i8 @negate_zero_or_minsigned(i8 %x) {
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; CHECK-LABEL: negate_zero_or_minsigned:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shlb $7, %al
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; CHECK-NEXT: # kill: def $al killed $al killed $eax
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; CHECK-NEXT: retq
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%signbit = shl i8 %x, 7
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%neg = sub i8 0, %signbit
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ret i8 %neg
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}
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define <4 x i32> @negate_zero_or_minsigned_vec(<4 x i32> %x) {
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; CHECK-LABEL: negate_zero_or_minsigned_vec:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: retq
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%signbit = and <4 x i32> %x, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>
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%neg = sub <4 x i32> zeroinitializer, %signbit
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ret <4 x i32> %neg
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}
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