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27 lines
1.4 KiB
Plaintext
27 lines
1.4 KiB
Plaintext
* Writing out ELF files is close to working but the following needs to
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be examined more closely:
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- Relocations use 2-byte / 4-byte to terminology in reference to
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the size of the immediate value being changed. The Xilinx
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terminology seems to be (???) 4-byte / 8-byte in reference
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to the number of bytes of instructions that are being changed.
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* Code generation seems to work relatively well now but the following
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needs to be examined more closely:
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- The stack layout needs to be examined to make sure it meets
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the standard, especially in regards to var arg functions.
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- The processor itineraries are copied from a different backend
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and need to be updated to model the MicroBlaze correctly.
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- Look at the MBlazeGenFastISel.inc stuff and make use of it
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if appropriate.
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* A basic assembly parser is present now and seems to parse most things.
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There are a few things that need to be looked at:
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- There are some instructions that are not generated by the backend
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and have not been tested as far as the parser is concerned.
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- The assembly parser does not use any MicroBlaze specific directives.
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I should investigate if there are MicroBlaze specific directive and,
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if there are, add them.
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- The instruction MFS and MTS use special names for some of the
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special registers that can be accessed. These special register
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names should be parsed by the assembly parser.
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