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0f36700d69
This allows the AArch64 backend to handle fadd, fsub, fmul and fdiv operations on f16 (half-precision) types by promoting to f32. llvm-svn: 215891
110 lines
1.7 KiB
LLVM
110 lines
1.7 KiB
LLVM
; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
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define half @add_h(half %a, half %b) {
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entry:
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; CHECK-LABEL: add_h:
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; CHECK: fcvt
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; CHECK: fcvt
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; CHECK: fadd
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; CHECK: fcvt
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%0 = fadd half %a, %b
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ret half %0
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}
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define half @sub_h(half %a, half %b) {
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entry:
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; CHECK-LABEL: sub_h:
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; CHECK: fcvt
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; CHECK: fcvt
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; CHECK: fsub
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; CHECK: fcvt
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%0 = fsub half %a, %b
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ret half %0
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}
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define half @mul_h(half %a, half %b) {
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entry:
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; CHECK-LABEL: mul_h:
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; CHECK: fcvt
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; CHECK: fcvt
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; CHECK: fmul
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; CHECK: fcvt
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%0 = fmul half %a, %b
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ret half %0
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}
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define half @div_h(half %a, half %b) {
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entry:
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; CHECK-LABEL: div_h:
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; CHECK: fcvt
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; CHECK: fcvt
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; CHECK: fdiv
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; CHECK: fcvt
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%0 = fdiv half %a, %b
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ret half %0
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}
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define half @load_h(half* %a) {
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entry:
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; CHECK-LABEL: load_h:
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; CHECK: ldr h
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%0 = load half* %a, align 4
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ret half %0
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}
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define void @store_h(half* %a, half %b) {
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entry:
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; CHECK-LABEL: store_h:
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; CHECK: str h
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store half %b, half* %a, align 4
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ret void
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}
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define half @s_to_h(float %a) {
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; CHECK-LABEL: s_to_h:
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; CHECK: fcvt
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%1 = fptrunc float %a to half
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ret half %1
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}
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define half @d_to_h(double %a) {
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; CHECK-LABEL: d_to_h:
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; CHECK: fcvt
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%1 = fptrunc double %a to half
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ret half %1
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}
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define float @h_to_s(half %a) {
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; CHECK-LABEL: h_to_s:
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; CHECK: fcvt
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%1 = fpext half %a to float
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ret float %1
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}
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define double @h_to_d(half %a) {
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; CHECK-LABEL: h_to_d:
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; CHECK: fcvt
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%1 = fpext half %a to double
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ret double %1
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}
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define half @bitcast_i_to_h(i16 %a) {
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; CHECK-LABEL: bitcast_i_to_h:
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; CHECK: fmov
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%1 = bitcast i16 %a to half
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ret half %1
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}
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define i16 @bitcast_h_to_i(half %a) {
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; CHECK-LABEL: bitcast_h_to_i:
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; CHECK: fmov
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%1 = bitcast half %a to i16
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ret i16 %1
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}
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