mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 04:22:57 +02:00
7a5c52fadf
LZCNT instructions are available. Force promotion to i32 to get a smaller encoding since the fix-ups necessary are just as complex for either promoted type We can't do standard promotion for CTLZ when lowering through BSR because it results in poor code surrounding the 'xor' at the end of this instruction. Essentially, if we promote the entire CTLZ node to i32, we end up doing the xor on a 32-bit CTLZ implementation, and then subtracting appropriately to get back to an i8 value. Instead, our custom logic just uses the knowledge of the incoming size to compute a perfect xor. I'd love to know of a way to fix this, but so far I'm drawing a blank. I suspect the legalizer could be more clever and/or it could collude with the DAG combiner, but how... ;] llvm-svn: 147251 |
||
|---|---|---|
| .. | ||
| ARM | ||
| CBackend | ||
| CellSPU | ||
| CPP | ||
| Generic | ||
| Hexagon | ||
| MBlaze | ||
| Mips | ||
| MSP430 | ||
| PowerPC | ||
| PTX | ||
| SPARC | ||
| Thumb | ||
| Thumb2 | ||
| X86 | ||
| XCore | ||