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401d9e7fdb
We may have subregister defs which are unused but not discovered and cleaned up prior to liveness analysis. This creates multiple connected components in the resulting live range which are forbidden in the MachineVerifier because they would unnecesarily constrain the register allocator. Rewrite those dead definitions to define a newly created virtual register. Differential Revision: http://reviews.llvm.org/D13035 llvm-svn: 248335
29 lines
1010 B
LLVM
29 lines
1010 B
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs -verify-coalescing < %s
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; The original and requires materializing a 64-bit immediate for
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; s_and_b64. This is split into 2 x v_and_i32, part of the immediate
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; is folded through the reg_sequence into the v_and_i32 operand, and
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; only half of the result is ever used.
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;
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; During live interval construction, the first sub register def is
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; incorrectly marked as dead.
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declare i32 @llvm.r600.read.tidig.x() #1
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define void @dead_def_subregister(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%val = load i64, i64 addrspace(1)* %in.gep
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%lshr = shl i64 %val, 24
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%and1 = and i64 %lshr, 2190433320969 ; (255 << 33) | 9
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%vec = bitcast i64 %and1 to <2 x i32>
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%elt1 = extractelement <2 x i32> %vec, i32 1
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store i32 %elt1, i32 addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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