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c00cb13f9c
This patch removes the PROC macro in favor of CPUKind enum and a table that contains information about CPUs. The current information in the table is the CPU name, CPUKind enum value, key feature for target multiversioning, and Is64Bit capable. For the strings that are aliases, I've duplicated the information in the table. This means there are more rows in the table than CPUKind enums. This replaces multiple StringSwitch's with loops through the table. They are linear searches due to the table being more logically ordered than alphabetical. The StringSwitch's would have also been linear. I've used StringLiteral on the strings in the table so we can quickly check the length while searching. I contemplated having a CPUKind for each string so there was a 1:1 mapping, but didn't want to spread more names to the places that use the enum. My ultimate goal here is to store the features for each CPU as a bitset within the table. Hoping to use constexpr to make this composable so we can group features and inherit them. After the table lookup we can turn the bitset into a list of strings for the frontend. The current switch we have for selecting features for CPUs has become difficult to maintain while trying to express inheritance relationships. Differential Revision: https://reviews.llvm.org/D82414
174 lines
7.4 KiB
C++
174 lines
7.4 KiB
C++
//===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise X86 hardware features.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Support/X86TargetParser.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/ADT/Triple.h"
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using namespace llvm;
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using namespace llvm::X86;
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namespace {
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struct ProcInfo {
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StringLiteral Name;
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X86::CPUKind Kind;
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unsigned KeyFeature;
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bool Is64Bit;
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};
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} // end anonymous namespace
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#define PROC_64_BIT true
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#define PROC_32_BIT false
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static constexpr ProcInfo Processors[] = {
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// i386-generation processors.
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{ {"i386"}, CK_i386, ~0U, PROC_32_BIT },
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// i486-generation processors.
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{ {"i486"}, CK_i486, ~0U, PROC_32_BIT },
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{ {"winchip-c6"}, CK_WinChipC6, ~0U, PROC_32_BIT },
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{ {"winchip2"}, CK_WinChip2, ~0U, PROC_32_BIT },
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{ {"c3"}, CK_C3, ~0U, PROC_32_BIT },
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// i586-generation processors, P5 microarchitecture based.
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{ {"i586"}, CK_i586, ~0U, PROC_32_BIT },
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{ {"pentium"}, CK_Pentium, ~0U, PROC_32_BIT },
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{ {"pentium-mmx"}, CK_PentiumMMX, ~0U, PROC_32_BIT },
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{ {"pentiumpro"}, CK_PentiumPro, ~0U, PROC_32_BIT },
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// i686-generation processors, P6 / Pentium M microarchitecture based.
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{ {"i686"}, CK_i686, ~0U, PROC_32_BIT },
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{ {"pentium2"}, CK_Pentium2, ~0U, PROC_32_BIT },
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{ {"pentium3"}, CK_Pentium3, ~0U, PROC_32_BIT },
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{ {"pentium3m"}, CK_Pentium3, ~0U, PROC_32_BIT },
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{ {"pentium-m"}, CK_PentiumM, ~0U, PROC_32_BIT },
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{ {"c3-2"}, CK_C3_2, ~0U, PROC_32_BIT },
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{ {"yonah"}, CK_Yonah, ~0U, PROC_32_BIT },
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// Netburst microarchitecture based processors.
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{ {"pentium4"}, CK_Pentium4, ~0U, PROC_32_BIT },
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{ {"pentium4m"}, CK_Pentium4, ~0U, PROC_32_BIT },
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{ {"prescott"}, CK_Prescott, ~0U, PROC_32_BIT },
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{ {"nocona"}, CK_Nocona, ~0U, PROC_64_BIT },
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// Core microarchitecture based processors.
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{ {"core2"}, CK_Core2, ~0U, PROC_64_BIT },
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{ {"penryn"}, CK_Penryn, ~0U, PROC_64_BIT },
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// Atom processors
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{ {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, PROC_64_BIT },
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{ {"atom"}, CK_Bonnell, FEATURE_SSSE3, PROC_64_BIT },
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{ {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, PROC_64_BIT },
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{ {"slm"}, CK_Silvermont, FEATURE_SSE4_2, PROC_64_BIT },
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{ {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, PROC_64_BIT },
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{ {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, PROC_64_BIT },
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{ {"tremont"}, CK_Tremont, FEATURE_SSE4_2, PROC_64_BIT },
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// Nehalem microarchitecture based processors.
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{ {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, PROC_64_BIT },
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{ {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, PROC_64_BIT },
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// Westmere microarchitecture based processors.
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{ {"westmere"}, CK_Westmere, FEATURE_PCLMUL, PROC_64_BIT },
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// Sandy Bridge microarchitecture based processors.
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{ {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, PROC_64_BIT },
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{ {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, PROC_64_BIT },
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// Ivy Bridge microarchitecture based processors.
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{ {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, PROC_64_BIT },
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{ {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, PROC_64_BIT },
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// Haswell microarchitecture based processors.
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{ {"haswell"}, CK_Haswell, FEATURE_AVX2, PROC_64_BIT },
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{ {"core-avx2"}, CK_Haswell, FEATURE_AVX2, PROC_64_BIT },
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// Broadwell microarchitecture based processors.
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{ {"broadwell"}, CK_Broadwell, FEATURE_AVX2, PROC_64_BIT },
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// Skylake client microarchitecture based processors.
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{ {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, PROC_64_BIT },
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// Skylake server microarchitecture based processors.
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{ {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, PROC_64_BIT },
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{ {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, PROC_64_BIT },
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// Cascadelake Server microarchitecture based processors.
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{ {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, PROC_64_BIT },
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// Cooperlake Server microarchitecture based processors.
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{ {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, PROC_64_BIT },
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// Cannonlake client microarchitecture based processors.
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{ {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, PROC_64_BIT },
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// Icelake client microarchitecture based processors.
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{ {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, PROC_64_BIT },
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// Icelake server microarchitecture based processors.
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{ {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, PROC_64_BIT },
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// Tigerlake microarchitecture based processors.
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{ {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, PROC_64_BIT },
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// Knights Landing processor.
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{ {"knl"}, CK_KNL, FEATURE_AVX512F, PROC_64_BIT },
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// Knights Mill processor.
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{ {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, PROC_64_BIT },
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// Lakemont microarchitecture based processors.
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{ {"lakemont"}, CK_Lakemont, ~0U, PROC_32_BIT },
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// K6 architecture processors.
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{ {"k6"}, CK_K6, ~0U, PROC_32_BIT },
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{ {"k6-2"}, CK_K6_2, ~0U, PROC_32_BIT },
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{ {"k6-3"}, CK_K6_3, ~0U, PROC_32_BIT },
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// K7 architecture processors.
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{ {"athlon"}, CK_Athlon, ~0U, PROC_32_BIT },
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{ {"athlon-tbird"}, CK_Athlon, ~0U, PROC_32_BIT },
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{ {"athlon-xp"}, CK_AthlonXP, ~0U, PROC_32_BIT },
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{ {"athlon-mp"}, CK_AthlonXP, ~0U, PROC_32_BIT },
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{ {"athlon-4"}, CK_AthlonXP, ~0U, PROC_32_BIT },
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// K8 architecture processors.
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{ {"k8"}, CK_K8, ~0U, PROC_64_BIT },
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{ {"athlon64"}, CK_K8, ~0U, PROC_64_BIT },
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{ {"athlon-fx"}, CK_K8, ~0U, PROC_64_BIT },
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{ {"opteron"}, CK_K8, ~0U, PROC_64_BIT },
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{ {"k8-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT },
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{ {"athlon64-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT },
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{ {"opteron-sse3"}, CK_K8SSE3, ~0U, PROC_64_BIT },
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{ {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, PROC_64_BIT },
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{ {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, PROC_64_BIT },
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// Bobcat architecture processors.
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{ {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, PROC_64_BIT },
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{ {"btver2"}, CK_BTVER2, FEATURE_BMI, PROC_64_BIT },
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// Bulldozer architecture processors.
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{ {"bdver1"}, CK_BDVER1, FEATURE_XOP, PROC_64_BIT },
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{ {"bdver2"}, CK_BDVER2, FEATURE_FMA, PROC_64_BIT },
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{ {"bdver3"}, CK_BDVER3, FEATURE_FMA, PROC_64_BIT },
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{ {"bdver4"}, CK_BDVER4, FEATURE_AVX2, PROC_64_BIT },
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// Zen architecture processors.
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{ {"znver1"}, CK_ZNVER1, FEATURE_AVX2, PROC_64_BIT },
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{ {"znver2"}, CK_ZNVER2, FEATURE_AVX2, PROC_64_BIT },
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// Generic 64-bit processor.
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{ {"x86-64"}, CK_x86_64, ~0U, PROC_64_BIT },
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// Geode processors.
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{ {"geode"}, CK_Geode, ~0U, PROC_32_BIT },
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};
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X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) {
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for (const auto &P : Processors)
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if (P.Name == CPU && (P.Is64Bit || !Only64Bit))
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return P.Kind;
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return CK_None;
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}
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void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values,
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bool Only64Bit) {
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for (const auto &P : Processors)
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if (P.Is64Bit || !Only64Bit)
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Values.emplace_back(P.Name);
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}
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ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) {
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// FIXME: Can we avoid a linear search here? The table might be sorted by
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// CPUKind so we could binary search?
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for (const auto &P : Processors) {
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if (P.Kind == Kind) {
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assert(P.KeyFeature != ~0U && "Processor does not have a key feature.");
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return static_cast<ProcessorFeatures>(P.KeyFeature);
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}
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}
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llvm_unreachable("Unable to find CPU kind!");
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}
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