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7a7f031d27
Move initGlobalBaseReg from MipsSEDAGToDAGISel to MipsFunctionInfo. This way functions used for handling position independent code during instruction selection, getGlobalBaseReg and initGlobalBaseReg, end up in same class. Differential Revision: https://reviews.llvm.org/D62586 llvm-svn: 362206
143 lines
5.8 KiB
C++
143 lines
5.8 KiB
C++
//===-- MipsSEISelDAGToDAG.h - A Dag to Dag Inst Selector for MipsSE -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsDAGToDAGISel specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H
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#define LLVM_LIB_TARGET_MIPS_MIPSSEISELDAGTODAG_H
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#include "MipsISelDAGToDAG.h"
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namespace llvm {
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class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
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public:
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explicit MipsSEDAGToDAGISel(MipsTargetMachine &TM, CodeGenOpt::Level OL)
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: MipsDAGToDAGISel(TM, OL) {}
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private:
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
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MachineFunction &MF);
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unsigned getMSACtrlReg(const SDValue RegIdx) const;
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bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);
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std::pair<SDNode *, SDNode *> selectMULT(SDNode *N, unsigned Opc,
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const SDLoc &dl, EVT Ty, bool HasLo,
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bool HasHi);
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void selectAddE(SDNode *Node, const SDLoc &DL) const;
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bool selectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset) const;
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bool selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
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unsigned OffsetBits,
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unsigned ShiftAmount) const;
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bool selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectAddrDefault(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddr(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectAddrRegImm9(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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bool selectAddrRegImm11(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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bool selectAddrRegImm12(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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bool selectAddrRegImm16(SDValue Addr, SDValue &Base,
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SDValue &Offset) const;
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bool selectIntAddr11MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddr12MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddr16MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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bool selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const override;
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/// Select constant vector splats.
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bool selectVSplat(SDNode *N, APInt &Imm,
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unsigned MinSizeInBits) const override;
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/// Select constant vector splats whose value fits in a given integer.
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bool selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
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unsigned ImmBitSize) const;
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/// Select constant vector splats whose value fits in a uimm1.
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bool selectVSplatUimm1(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a uimm2.
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bool selectVSplatUimm2(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a uimm3.
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bool selectVSplatUimm3(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a uimm4.
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bool selectVSplatUimm4(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a uimm5.
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bool selectVSplatUimm5(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a uimm6.
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bool selectVSplatUimm6(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a uimm8.
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bool selectVSplatUimm8(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value fits in a simm5.
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bool selectVSplatSimm5(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value is a power of 2.
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bool selectVSplatUimmPow2(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value is the inverse of a
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/// power of 2.
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bool selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value is a run of set bits
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/// ending at the most significant bit
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bool selectVSplatMaskL(SDValue N, SDValue &Imm) const override;
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/// Select constant vector splats whose value is a run of set bits
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/// starting at bit zero.
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bool selectVSplatMaskR(SDValue N, SDValue &Imm) const override;
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bool trySelect(SDNode *Node) override;
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void processFunctionAfterISel(MachineFunction &MF) override;
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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unsigned ConstraintID,
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std::vector<SDValue> &OutOps) override;
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};
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FunctionPass *createMipsSEISelDag(MipsTargetMachine &TM,
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CodeGenOpt::Level OptLevel);
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}
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#endif
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